MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 31

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page)
NOTE: 1. This table applies when CKE
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
CURRENT STATE CS# RAS# CAS# WE#
Precharging
(With Auto
(With Auto
Activating,
Precharge)
Precharge)
Precharge
Precharge
Disabled)
Disabled)
Active, or
(Auto
(Auto
Write
Write
Read
Read
Row
Any
Idle
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the
3. Current state definitions:
previous state was self refresh).
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when
Write w/Auto
Read w/Auto
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Row Active: A row in the bank has been activated, and
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
Idle: The bank has been precharged, and
H
H
H
H
H
X
H
X
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
no register accesses are in progress.
or been terminated.
or been terminated.
t
t
RP has been met. Once
RP has been met. Once
n-1
was HIGH and CKE
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
COMMAND (ACTION)
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
PRECHARGE
ACTIVE (Select and activate row)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
WRITE (Select column and start WRITE burst)
READ (Select column and start new READ burst)
READ (Select column and start READ burst)
PRECHARGE
PRECHARGE
(Continued on next page)
n
t
t
RP is met, the bank will be in the idle state.
RP is met, the bank will be in the idle state.
is HIGH (see Truth Table 2) and after
31
t
RP has been met.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD has been met. No data bursts/accesses and
128Mb: x4, x8, x16
t
XSR has been met (if the
©2001, Micron Technology, Inc.
SDRAM
7, 8, 14
7, 8, 15
7, 8, 16
7, 8, 17
NOTES
7, 10
7, 11
7, 12
7, 13
7
7
9
9
9
9