MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 40

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TIMING PARAMETERS
*CAS latency indicated in parentheses.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.
SYMBOL*
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
DQML, DQMH
A0-A9, A11
COMMAND
DQM /
BA0, BA1
CKE
CLK
A10
DQ
MIN
0.8
1.5
2.5
2.5
7.5
7
Precharge all
High-Z
t CKS
t CMS
active banks
-7E
t AS
SINGLE BANK
ALL BANKS
PRECHARGE
BANK(S)
MAX
T0
t AH
t CKH
t CMH
t CK
MIN
0.8
1.5
2.5
2.5
7.5
10
-75
MAX
t RP
T1
NOP
MIN
10
1
2
3
3
8
-8E
AUTO REFRESH MODE
MAX
REFRESH
T2
AUTO
t CH
UNITS
ns
ns
ns
ns
ns
ns
t RFC
40
NOP
1
(
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(
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(
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(
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)
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NOP
SYMBOL* MIN
t
t
t
t
t
t
CKH
CKS
CMH
CMS
RFC
RP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t CL
Tn + 1
REFRESH
0.8
1.5
0.8
1.5
66
15
AUTO
-7E
MAX
t RFC
128Mb: x4, x8, x16
NOP
1
MIN
0.8
1.5
0.8
1.5
66
20
(
(
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)
)
(
)
(
)
)
-75
NOP
MAX
MIN
To + 1
70
20
1
2
1
2
©2001, Micron Technology, Inc.
ACTIVE
ROW
ROW
BANK
SDRAM
-8E
DON’T CARE
MAX
UNITS
ns
ns
ns
ns
ns
ns