MT48LC32M4A2FC-8ELIT MICRON [Micron Technology], MT48LC32M4A2FC-8ELIT Datasheet - Page 22

• Manufacturer Part Number: MT48LC32M4A2FC-8ELIT
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

WRITEs
as shown in Figure 13.
vided with the WRITE command, and auto precharge is
either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.
will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each
successive positive clock edge. Upon completion of a
fixed-length burst, assuming no other commands have
been initiated, the DQs will remain High-Z and any addi-
tional input data will be ignored (see Figure 14). A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to column 0 and continue.)
subsequent WRITE command, and data for a fixed-length
WRITE burst may be immediately followed by data for a
WRITE command. The new WRITE command can be
issued on any clock following the previous WRITE com-
mand, and the data provided coincident with the new
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
WRITE bursts are initiated with a WRITE command,
During WRITE bursts, the first valid data-in element
Data for any WRITE burst may be truncated with a
A0-A9, A11: x4
The starting column and bank addresses are pro-
A9, A11: x16
A0-A9: x8
A0-A8: x16
A11: x8
BA0,1
CAS#
RAS#
WE#
A10
CLK
CKE
CS#
WRITE Command
HIGH
Figure 13
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
COLUMN
ADDRESS
ADDRESS
BANK
22
command applies to the new command. An example is
shown in Figure 15. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. The 128Mb
SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch archi-
tecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed
random write accesses within a page can be performed to
the same bank, as shown in Figure 16, or each subsequent
WRITE may be performed to a different bank.
COMMAND
ADDRESS
NOTE:
COMMAND
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ADDRESS
CLK
DQ
NOTE:
CLK
DQ
Burst length = 2. DQM is LOW.
WRITE
BANK,
COL n
WRITE to WRITE
T0
D
n
IN
WRITE Burst
DQM is LOW. Each WRITE
command may be to any bank.
WRITE
BANK,
COL n
Figure 14
Figure 15
D
128Mb: x4, x8, x16
T0
n
IN
NOP
n + 1
T1
D
IN
n + 1
NOP
T1
D
IN
DON’T CARE
NOP
T2
©2001, Micron Technology, Inc.
SDRAM
WRITE
BANK,
COL b
T2
D
b
IN
T3
NOP