h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 726

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 20 ROM
Rev. 5.00 Sep 22, 2005 page 700 of 1136
REJ09B0257-0500
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be
Reprogram Data Computation Table
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See note 6 for details of the pulse widths.
7. The wait times and value of N are shown in section 23.7, Flash Memory Characteristics.
Original Data
H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes;
in this case, H'FF data must be written to the extra addresses.
the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop.
Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
When writing of additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
(D)
0
0
1
1
Figure 20.11 Program/Program-Verify Flowchart (128-Byte Programming)
Note: Use a 10 µs write pulse for additional programming.
Note 6. Write Pulse Width
Number of Writes n
Verify Data
Write pulse application subroutine
1000
998
999
10
11
12
13
Clear PSU bit in FLMCR1
Reprogram data storage
Additional-programming
1
2
3
4
5
6
7
8
9
Sub-Routine Write Pulse
(V)
Set PSU bit in FLMCR1
Program data storage
Clear P bit in FLMCR1
0
1
0
1
Set P bit in FLMCR1
data storage area
area (128 bytes)
area (128 bytes)
Wait (t
Wait (t
(128 bytes)
WDT enable
Wait (t
Wait (t
Disable WDT
RAM
End Sub
spsu
cpsu
Reprogram Data
Write Time (tsp) µsec
sp
cp
) µs
) µs
) µs
) µs
(X)
1
0
1
1
200
200
200
200
200
200
200
200
200
200
30
30
30
30
30
30
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
*
*
*
*
Start of programming
End of programming
7
5
7
7
*
7
Comments
Increment address
Additional-Programming Data Computation Table
Successively write 128-byte data from additional-
Reprogram Data
programming data area in RAM to flash memory
No
Transfer reprogram data to reprogram data area
Additional-programming data computation
Write Pulse (Additional programming)
Transfer additional-programming data to
Store 128-byte program data in program
(X')
data area consecutively to flash memory
Write 128-byte data in RAM reprogram
0
0
1
1
H'FF dummy write to verify address
data area and reprogram data area
additional-programming data area
Clear SWE bit in FLMCR1
Reprogram data computation
data verification completed?
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
Wait (t
Wait (t
Read verify data
Wait (t
Wait (t
Wait (t
Yes
Yes
Verify Data
Write data =
Write pulse
verify data?
Yes
128-byte
START
m = 0?
m = 0
n = 1
6 n?
6 n?
(V)
sswe
cswe
spvr
0
1
0
1
spv
cpv
Yes
Yes
Sub-Routine-Call
Sub-Routine-Call
) µs
) µs
) µs
) µs
) µs
Programming Data (Y)
Additional-
No
No
No
0
1
1
1
*
*
*
*
No
*
*
7
See note 6 for pulse width
7
7
2
3
7
*
*
*
4
1
4
*
*
m = 1
1
4
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Clear SWE bit in FLMCR1
Additional programming to be executed
Additional programming not to be executed
Additional programming not to be executed
Additional programming not to be executed
Programming failure
Wait (t
n
cswe
(N)?
Yes
) µs
Comments
*
7
No
n
n + 1
*
Reprogram
7