h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 13

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

7.6
7.7
7.8
7.9
Section 8 Data Transfer Controller (DTC)
8.1
8.2
8.3
8.4
7.5.2
7.5.3
Idle Cycle.......................................................................................................................... 172
7.6.1
7.6.2
Write Data Buffer Function .............................................................................................. 177
Bus Arbitration ................................................................................................................. 178
7.8.1
7.8.2
7.8.3
Resets and the Bus Controller........................................................................................... 179
Overview .......................................................................................................................... 181
8.1.1
8.1.2
8.1.3
Register Descriptions........................................................................................................ 184
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Operation .......................................................................................................................... 192
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10 Number of DTC Execution States ....................................................................... 207
8.3.11 Procedures for Using DTC .................................................................................. 209
8.3.12 Examples of Use of the DTC............................................................................... 210
Interrupts........................................................................................................................... 213
Basic Timing........................................................................................................ 170
Wait Control ........................................................................................................ 172
Operation ............................................................................................................. 172
Pin States During Idle Cycles .............................................................................. 176
Overview ............................................................................................................. 178
Operation ............................................................................................................. 178
Bus Transfer Timing............................................................................................ 178
Features................................................................................................................ 181
Block Diagram..................................................................................................... 182
Register Configuration......................................................................................... 183
DTC Mode Register A (MRA) ............................................................................ 184
DTC Mode Register B (MRB)............................................................................. 186
DTC Source Address Register (SAR).................................................................. 187
DTC Destination Address Register (DAR).......................................................... 187
DTC Transfer Count Register A (CRA) .............................................................. 188
DTC Transfer Count Register B (CRB)............................................................... 188
DTC Enable Registers (DTCER)......................................................................... 189
DTC Vector Register (DTVECR)........................................................................ 190
Module Stop Control Register A (MSTPCRA) ................................................... 191
Overview ............................................................................................................. 192
Activation Sources............................................................................................... 194
DTC Vector Table ............................................................................................... 196
Location of Register Information in Address Space ............................................ 200
Normal Mode....................................................................................................... 201
Repeat Mode........................................................................................................ 202
Block Transfer Mode........................................................................................... 203
Chain Transfer ..................................................................................................... 205
Operation Timing ................................................................................................ 206
.................................................................. 181
Rev. 5.00 Sep 22, 2005 page xiii of xxvi