h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 479

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in
asynchronous mode, causing abnormal termination.
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is
Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity
addition in asynchronous mode, causing abnormal termination.
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is
Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of
the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 4
FER
0
1
Bit 3
PER
0
1
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not
cleared to 0.
is not checked. If a framing error occurs, the receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial reception cannot be continued while the
FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be
continued, either.
cleared to 0.
set. Also, subsequent serial reception cannot be continued while the PER flag is set to
1. In clocked synchronous mode, serial transmission cannot be continued, either.
Description
[Clearing condition]
When 0 is written to FER after reading FER = 1
[Setting condition]
When the SCI checks whether the stop bit at the end of the receive data when
reception ends, and the stop bit is 0 *
Description
[Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit does not
match the parity setting (even or odd) specified by the O/E bit in SMR *
Section 13 Serial Communication Interface (SCI)
2
Rev. 5.00 Sep 22, 2005 page 453 of 1136
REJ09B0257-0500
2
(Initial value) *
(Initial value) *
1
1