h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 454

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 12 Watchdog Timer
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from
H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the
H8S/2646 Group if TCNT overflows during watchdog timer operation.
Note: * The modules within the H8S/2646 Group are not reset, but TCNT and TCSR within the
Bit 5—Reserved: Always read as 0. Can only be written with 0.
Bits 4 to 0—Reserved: Always read as 1. Not writable.
Rev. 5.00 Sep 22, 2005 page 428 of 1136
REJ09B0257-0500
Bit 7
WOVF
0
1
Bit 6
RSTE
0
1
WDT are reset.
see section 12.2.4, Notes on Register Access.
Description
[Clearing condition]
Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF
[Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
Description
Reset signal is not generated if TCNT overflows *
Reset signal is generated if TCNT overflows
(Initial value)
(Initial value)