h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 662

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 17 Motor Control PWM Timer
17.2.7
There are four 16-bit read/write PWBFR1 registers (PWBFR1A, 1C, 1E, 1G). When a PWCYR1
compare match occurs, data is transferred from PWBFR1A to PWDTR1A, from PWBFR1C to
PWDTR1C, from PWBFR1E to PWDTR1E, and from PWBFR1G to PWDTR1G.
PWBFR1 is initialized to H'EC00 upon reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 15 to 13—Reserved: These bits are always read as 1 and cannot be modified.
Bit 12—Output Terminal Select (OTS): Bit 12 is the data transferred to bit 12 of PWDTR1.
Bits 11 and 10—Reserved: These bits are always read as 1 and cannot be modified.
Bits 9 to 0—Duty (DT): Bits 9 to 0 comprise the data transferred to bits 9 to 0 in PWDTR1.
17.2.8
There are eight PWDTR2 registers (PWDTR2A to PWDTR2H). PWDTR2A is used for output
PWM2A, PWDTR2B for output PWM2B, PWDTR2C for output PWM2C, PWDTR2D for output
PWM2D, PWDTR2E for output PWM2E, PWDTR2F for output PWM2F, PWDTR2G for output
PWM2G, and PWDTR2H for output PWM2H.
PWDTR2 cannot be read or written to directly. When a PWCYR2 compare match occurs, data is
transferred from buffer register 2 (PWBFR2) to PWDTR2.
PWDTR2 is initialized to H'EC00 when the counter start bit (CST) in PWCR2 is cleared to 0, and
also upon reset and in standby mode, watch mode, subactive mode, subsleep mode, and module
stop mode.
Rev. 5.00 Sep 22, 2005 page 636 of 1136
REJ09B0257-0500
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
PWM Buffer Registers 1A, 1C, 1E, 1G (PWBFR1A, 1C, 1E, 1G)
PWM Duty Registers 2A to 2H (PWDTR2A to PWDTR2H)
15
15
—
—
—
—
1
1
14
14
—
—
—
—
1
1
13
13
— OTS —
— R/W —
—
—
1
1
12
12
—
—
0
0
11
11
—
—
1
1
10
10
— DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
— R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
— DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
—
1
1
—
9
0
9
0
—
8
0
8
0
—
7
0
7
0
—
6
0
6
0
—
5
0
5
0
—
4
0
4
0
—
3
0
3
0
—
2
0
2
0
—
1
0
1
0
—
0
0
0
0