h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 149

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
5.5.2
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.5.3
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Instructions that Disable Interrupts
Times when Interrupts are Disabled
Figure 5.8 Contention between Interrupt Generation and Disabling
TIER0 write cycle by CPU
TIER0 address
Rev. 5.00 Sep 22, 2005 page 123 of 1136
TCIV exception handling
Section 5 Interrupt Controller
REJ09B0257-0500