h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 462

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h8s-2646

Manufacturer Part Number
h8s-2646
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 12 Watchdog Timer
12.5.2
If bits PSS and CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could
occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0)
before changing the value of bits PSS and CKS2 to CKS0.
12.5.3
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
12.5.4
In watchdog timer mode, the H8S/2646 Group will not be reset internally if TCNT overflows
while the RSTE bit is cleared to 0. When this module is used as a watchdog timer, the RSTE bit
must be set to 1 beforehand.
12.5.5
When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0
to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there
is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is
polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before
writing 0 to the OVF bit to clear the flag.
Rev. 5.00 Sep 22, 2005 page 436 of 1136
REJ09B0257-0500
Changing Value of PSS and CKS2 to CKS0
Switching between Watchdog Timer Mode and Interval Timer Mode
Internal Reset in Watchdog Timer Mode
OVF Flag Clearing in Interval Timer Mode

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