h8s-2646 Renesas Electronics Corporation., h8s-2646 Datasheet - Page 450

• Manufacturer Part Number: h8s-2646
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 12 Watchdog Timer
Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00.
In interval timer mode, the OVF flag can be cleared in the interval timer interrupt service routine
by reading TCSR while OVF = 1, then writing 0 to OVF, in accordance with the OVF flag
clearing conditions.
However, if conflict occurs between the OVF flag setting timing and OVF flag read timing when
interval timer interrupts are disabled and the OVF flag is polled, it has been found that in some
cases the read of OVF = 1 is not recognized.
In this case, the OVF flag clearing conditions can be reliably met by reading the OVF = 1 state
two or more times. In the above example, therefore, the OVF = 1 state should be read at least
twice before clearing the OVF flag.
Bit 6—Timer Mode Select (WT/IT IT IT IT): Selects whether the WDT is used as a watchdog timer or
interval timer. When TCNT overflows, WDT0 issues an internal reset if bit RSTE of the reset
control/status register (RSTCSR) is set to 1. In the interval timer mode, WDT0 sends a WOVI
interrupt request to the CPU. WDT1, on the other hand, requests a reset or an NMI interrupt from
the CPU if the watchdog timer mode is chosen, whereas it requests a WOVI interrupt from the
CPU if the interval timer mode is chosen.
• WDT0 Mode Select
Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR).
Rev. 5.00 Sep 22, 2005 page 424 of 1136
REJ09B0257-0500
Bit 7
OVF
0
1
TCSR0
WT/IT IT IT IT
0
1
Description
[Clearing conditions]
•
•
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset.
Description
Interval timer mode: WDT0 requests an interval timer interrupt (WOVI)
from the CPU when the TCNT overflows.
Watchdog timer mode: A reset is issued when the TCNT overflows if the RSTE bit of
RSTCSR is set to 1. *
Cleared when 0 is written to the TME bit (Only applies to WDT1)
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
(Initial value)
(Initial value)