or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 78

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

ORCA OR3LxxxB Series FPGAs
Package Thermal Characteristics
There are four thermal parameters that are in common
use: Θ
the parameters are affected, to varying degrees, by
package design (including paddle size) and choice of
materials, the amount of copper in the test board or
system board, and system airflow.
Table 32 contains the currently available thermal speci-
fications for Lattice’s FPGA packages mounted on both
JEDEC and non-JEDEC test boards. The thermal val-
ues for the newer package types correspond to those
packages mounted on a JEDEC four-layer board. The
values for the older packages, however, correspond to
those packages mounted on a non-JEDEC, single-
layer, sparse copper board (see Note 2). It should also
be noted that the values for the older packages are
considered conservative.
Θ Θ Θ Θ
This is the thermal resistance from junction to ambient
(a.k.a. Θ-
where T
air temperature, and Q is the chip power.
Experimentally, Θ
mal test die is assembled into the package of interest,
and the part is mounted on the thermal test board. The
diodes on the test chip are separately calibrated in an
oven. The package/board is placed either in a JEDEC
natural convection box or in the wind tunnel, the latter
for forced convection measurements. A controlled
amount of power (Q) is dissipated in the test chip’s
heater resistor, the chip’s temperature (T
mined by the forward drop on the diodes, and the ambi-
ent temperature (T
expressed in units of °C/watt.
78
JA
JA,
J
JA
ψ
is the junction temperature, T
JC,
, R-Θ, etc.). It is defined by the following:
Θ
JC, and
JA
A
) is noted. Note that Θ
is determined when a special ther-
Θ
JA
Θ
JB
=
. It should be noted that all
T
------------------- -
J
Q
–
T
A
A
is the ambient
J
) is deter-
JA
is
ψ ψ ψ ψ
This JEDEC designated parameter correlates the junc-
tion temperature to the case temperature. It is generally
used to infer the junction temperature while the device
is operating in the system. It is not considered a true
thermal resistance, and it is defined by the following:
where T
T
During the Θ
besides the other parameters measured, an additional
temperature reading, T
attached at top-dead-center of the case. ψ
expressed in units of °C/watt.
Θ Θ Θ Θ
This is the thermal resistance from junction to case. It
is most often used when attaching a heat sink to the
top of the package. It is defined by the following:
The parameters in this equation have been defined
above. However, the measurements are performed with
the case of the part pressed against a water-cooled
heat sink so as to draw most of the heat generated by
the chip out the top of the package. It is this difference
in the measurement process that differentiates Θ
from ψ
expressed in units of °C/watt.
Θ Θ Θ Θ
This is the thermal resistance from junction to board
(a.k.a. Θ
where T
lead measured with a thermocouple. The other param-
eters on the right-hand side have been defined above.
This is considered a true thermal resistance, and the
measurement is made with a water-cooled heat sink
pressed against the board so as to draw most of the
heat out of the leads. Note that Θ
units of °C/watt, and that this parameter and the way it
is measured is still in JEDEC committee.
J
JC
JC
JB
is the junction temperature, and Q is the chip power.
JC.
C
B
JL
Θ
is the temperature of the board adjacent to a
is the case temperature at top dead center,
). It is defined by the following:
JC
JA
is a true thermal resistance and is
measurements described above,
ψ
JC
Θ
Θ
JC
C
=
JB
, is made with a thermocouple
T
------------------- -
=
=
J
T
------------------- -
Q
–
T
------------------- -
J
T
J
Q
–
C
Q
–
T
Lattice Semiconductor
T
JB
C
Data Addendum
B
is expressed in
March 2002
JC
is also
JC