or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 23

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

Data Addendum
March 2002
Lattice Semiconductor
Timing Characteristics
Special Function Blocks Timing
Table 13. Microprocessor Interface (MP I) Timing Characteristics
OR3LxxB Commercial: V
to 3.6 V, V
10. User should set up read data so that RDS_SET and RDS_HLD can be met for the microprocessor timing.
Notes:
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA.
PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).
PowerPC Interface Timing (T
i960 Interface Timing (T
1. For user system flexibility, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
5. User Logic Delay has no predefined value. The user must generate a UEND signal to complete the cycle.
6. USTART_DEL is based on the falling clock edge.
7. There is no specific time associated with this delay. The user must assert UEND low to complete this cycle.
8. The user must assert interrupt request low until a service routine is executed.
9. This should be at least one MPI_CLK cycle.
RDYRCV_DELZ
RDYRCV_DEL
URDWR_DEL
when MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and
CS1 may go inactive before the end of the read/write cycle.
ADSN_HLD
ADSN_SET
TA_DELZ
WD_SET
WD_HLD
RW_SET
RW_HLD
WD_SET
WD_HLD
BI_DELZ
CS_SET
CS_HLD
BE_HLD
UA_DEL
BE_SET
TA_DEL
Symbol
BI_DEL
A_HLD
A_HLD
A_SET
A_SET
DD
2 = 2.38 V to 2.63 V, –40 °C
Transfer Acknowledge Delay (CLK to TA)
Burst Inhibit Delay (CLK to BIN)
Transfer Acknowledge Delay to High Impedance
Burst Inhibit Delay to High Impedance
Write Data Setup Time (data to TS)
Write Data Hold Time (data from CLK while MPI_ACK low)
Address Setup Time (addr to TS)
Address Hold Time (addr from CLK while MPI_ACK low)
Read/Write Setup Time (R/W to TS)
Read/Write Hold Time (R/W from CLK while MPI_ACK low)
Chip Select Setup Time (CS0, CS1 to TS)
Chip Select Hold Time (CS0, CS1 from CLK)
User Address Delay (pad to UA[3:0])
User Read/Write Delay (pad to URDWR_DEL)
Addr/Data Select to ALE (ADS, to ALE low)
Addr/Data Select to ALE (ADS, from ALE low)
Ready/Receive Delay (CLK to RDYRCV)
Ready/Receive Delay to High Impedance
Write Data Setup Time
Write Data Hold Time
Address Setup Time (addr to ALE low)
Address Hold Time (addr from ALE low)
Byte Enable Setup Time (BE0, BE1 to ALE low)
Byte Enable Hold Time (BE0, BE1 from ALE low)
DD
J
= 85 °C, V
= 3.0 V to 3.6 V, V
J
(continued)
= 85 °C, V
DD
= min, V
<
4
T
DD
3
A
Parameter
DD
<
= min, V
+85 °C.
2 = 2.38 V to 2.63 V, 0 °C
DD
2 = min)
DD
2 = min)
2
2
2
ORCA OR3LxxxB Series FPGAs
<
T
A
<
0.46
0.80
0.80
Min Max Min Max
70 °C; Industrial: V
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
—
—
—
—
—
—
—
—
—
—
—
—
—
–7
9.50
9.40
2.20
4.60
9.50
0.12
0.12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.40
0.70
0.70
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
—
—
—
—
—
—
—
—
—
—
—
—
—
–8
DD
8.30
8.20
1.90
4.00
8.30
0.10
0.10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
= 3.0 V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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