or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 34

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

ORCA OR3LxxxB Series FPGAs
Timing Characteristics
Table 21. OR3Lxxx Input to General System Clock (SCLK) Setup/Hold Time (Pin-to-Pin)
OR3LxxB Commercial: V
to 3.6 V, V
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the clock network. It includes both the input buffer
34
delay and the clock routing to the PIO FF CLK input. The delay will be reduced if any of the clock branches
are not used. The given setup (delayed and no delay) and hold (delayed) timing allows the input clock pin
to be located in any PIO on any side of the device, but a PIO FF must be used. The hold (no delay) timing
assumes the clock pin is located at one of the four middle PICs on any side of the device and that a PIO FF
is used. If the clock pin is located elsewhere, then the last parameter in the table must be added to the hold
(no delay) timing.
Input to SCLK Setup Time
Input to SCLK Setup Time (delayed
data input)
Input to SCLK Hold Time
Input to SCLK Hold Time (delayed data
input)
Additional Hold Time if Non-mid-PIC
Used as SCLK Pin
(no delay on data input)
(T
J
= 85 °C, V
DD
2 = 2.38 V to 2.63 V, –40 °C
Description
DD
= min, V
DD
DD
= 3.0 V to 3.6 V, V
2 = min)
Figure 11. Input to System Clock Setup/Hold Time
(continued)
INPUT
CLK
<
T
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
A
Device
DD
<
+85 °C.
2 = 2.38 V to 2.63 V, 0 °C
CLKCNTRL
5.69
5.57
6.46
6.96
1.04
1.43
Min
0.0
0.0
0.0
0.0
ECLK
PIO ECLK LATCH
-7
Max
—
—
—
—
—
—
—
—
—
—
D
Q
5.07
4.96
5.67
6.16
1.03
1.43
Min
0.0
0.0
0.0
0.0
<
T
-8
A
<
Max
—
—
—
—
—
—
—
—
—
—
70 °C; Industrial: V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Lattice Semiconductor
Data Addendum
March 2002
DD
= 3.0 V
5-4847 (F)