or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 26

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

ORCA OR3LxxxB Series FPGAs
Timing Characteristics
Table 15. General-Purpose Clock Timing Characteristics (Internally Generated Clock)
OR3LxxB Commercial: V
to 3.6 V, V
Notes:
This table represents the delay for an internally generated clock from the clock tree input in one of the four middle
PICs (using pSW routing) on any side of the device which is then distributed to the PFU/PIO clock inputs. If the clock
tree input used is located at any other PIC, see the results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the general clock network. The delay will be reduced if any of
the clock branches are not used. See pin-to-pin timing in Table 18 for clock delays of clocks input on general I/O pins.
26
CLK_DEL
CLK_DEL
Symbol
DD
2 = 2.38 V to 2.63 V, –40 °C
(T
J
= 85 °C, V
DD
OR3L165
OR3L225
DD
= 3.0 V to 3.6 V, V
Device
= min, V
(continued)
DD
<
2 = min)
T
A
DD
<
+85 °C.
2 = 2.38 V to 2.63 V, 0 °C
Min
—
—
-7
Max
4.56
4.58
Min
—
—
<
-8
T
A
Max
3.98
3.99
<
70 °C; Industrial: V
Unit
ns
ns
Lattice Semiconductor
Data Addendum
March 2002
DD
= 3.0 V