or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 27

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

Data Addendum
March 2002
Lattice Semiconductor
Timing Characteristics
Table 16. OR3Lxxx ExpressCLK to Output Delay (Pin-to-Pin)
OR3LxxB Commercial: V
to 3.6 V, V
Notes:
Timing is without the use of the PCM.
This clock delay is for a fully routed clock tree that uses the ExpressCLK network. It includes both the input
buffer delay, the clock routing to the PIO CLK input, the clock→Q of the FF, and the delay through the output
buffer. The given timing requires that the input clock pin be located at one of the six ExpressCLK inputs of the
device, and that a PIO FF be used.
ECLK Middle Input Pin→OUTPUT
Pin (Fast)
ECLK Middle Input Pin→OUTPUT
Pin (Slewlim)
ECLK Middle Input Pin→OUTPUT
Pin (Sinklim)
Additional Delay if ECLK Corner Pin
Used
(T
J
= 85 °C, V
DD
2 = 2.38 V to 2.63 V, –40 °C
Description
DD
= min, V
DD
DD
= 3.0 V to 3.6 V, V
2 = min)
(continued)
ECLK
Figure 6. ExpressCLK to Output Delay
<
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
OR3L165
OR3L225
Device
T
A
DD
<
+85 °C.
D
2 = 2.38 V to 2.63 V, 0 °C
PIO FF
Q
Min
—
—
—
—
—
—
—
—
-7
12.91
12.96
OUTPUT (50 pF LOAD)
Max
6.94
6.99
7.79
7.84
2.70
2.90
Min
—
—
—
—
—
—
—
—
ORCA OR3LxxxB Series FPGAs
-8
<
11.08
11.13
Max
5.84
5.89
6.64
6.69
2.21
2.38
T
A
<
70 °C; Industrial: V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
DD
= 3.0 V
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