or3l165b Lattice Semiconductor Corp., or3l165b Datasheet

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or3l165b

Manufacturer Part Number
or3l165b
Description
Orca Or3lxxxb Series Field-programmable Gate Arrays
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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March 2002
Introduction
This data addendum refers to the information found
in the ORCA
Gate Arrays Data Sheet.
Features
Table 1. ORCA OR3LxxxB Series FPGAs
‡ The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (three FFs, fast-capture latch, output
logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32
(or 512 gates) per PFU.
High-performance, cost-effective, 0.25 µm 5-level
metal technology.
2.5 V internal supply voltage and 3.3 V I/O supply
voltage for speed and compatibility.
Up to 340,000 usable gates
Up to 612 user I/Os in 0.25 µm. (OR3LxxxB I/Os
are 5 V tolerant to allow interconnection to both
3.3 V and 5 V devices, selectable on a per-pin
basis, when using 3.3 V I/O supply.)
Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables (LUTs)
per PFU, organized in two nibbles for use in nibble-
or byte-wide functions. Allows for mixed arithmetic
and logic functions in a single PFU.
Nine user registers per PFU, one following each
LUT, plus one extra. All have programmable clock
enable and local set/reset, plus a global set/reset
that can be disabled per PFU.
Flexible input structure (FINS) of the PFUs pro-
vides a routability enhancement for LUTs with
OR3L165B
OR3L225B
Device
®
Series 3C and 3T Field-Programmable
120K—244K
166K—340K
System
Gates
in 0.25 µm.
11552
LUTs
8192
Registers
10752
14820
Field-Programmable Gate Arrays
Max User
* PAL is a trademark of Lattice Semiconductor
† IEEE is a registered trademark of The Institute of Electrical and
RAM
131K
185K
Electronics Engineers, Inc.
shared inputs and the logic flexibility of LUTs with
independent inputs.
Fast-carry logic and routing to adjacent PFUs for
nibble-wide, byte-wide, or longer arithmetic func-
tions, with the option to register the PFU carry-out.
Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU.
Supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and PAL *-like AND-OR-INVERT (AOI) in each pro-
grammable logic cell (PLC).
Abundant hierarchical routing resources based on
routing two data nibbles and two control lines per
set provide for faster place and route implementa-
tions and less routing delay.
Individually programmable drive capability: 12 mA
sink/6 mA source or 6 mA sink/3 mA source.
Built-in boundary scan ( IEEE
testability function to 3-state all I/O pins.
Enhanced system clock routing for low-skew, high-
speed clocks originating on-chip or at any I/O.
Up to four ExpressCLK inputs allow extremely fast
clocking of signals on- and off-chip plus access to
internal general clock routing.
StopCLK feature to glitchlessly stop/start the
ExpressCLKs independently by user command.
ORCA
User I/Os Array Size
516
612
®
OR3LxxxB Series
32
38
×
×
32
38
1149.1 JTAG) and
0.25 µm/5 LM
0.25 µm/5 LM
Technology
Process
×
4 RAM

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or3l165b Summary of contents

Page 1

... Table 1. ORCA OR3LxxxB Series FPGAs System Device ‡ Gates OR3L165B 120K—244K OR3L225B 166K—340K ‡ The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU) ...

Page 2

ORCA OR3LxxxB Series FPGAs Contents Introduction................................................................ 1 Features .................................................................... 1 System-Level Features.............................................. 4 Support...................................................................... 5 Description ................................................................ 5 FPGA Overview ...................................................... 5 PLC Logic ............................................................... 5 PIC Logic ................................................................ 8 System Features ..................................................... 9 Routing.................................................................... 9 Configuration........................................................... 9 Configuration Data ...

Page 3

Data Addendum March 2002 Figure Figure 1. Simplified PFU Diagram ............................... 6 Figure 2. SLIC All Modes Diagram .............................. 7 Figure 3. OR3Lxxx Programmable Input/Output Image from ORCA Foundry.................................... 8 Figure 4. Synchronous Memory Write Characteristics ............................................ 17 Figure 5. ...

Page 4

ORCA OR3LxxxB Series FPGAs Features (continued) Programmable I/O (PIO) has: — Fast-capture input latch and input flip-flop (FF)/ latch for reduced input setup time and zero hold time. — Capability to (de)multiplex I/O signals. — Fast access to SLIC for ...

Page 5

Data Addendum March 2002 Support ORCA Foundry development system support. Supported by industry-standard CAE tools for design entry, synthesis, simulation, and timing analysis. Description FPGA Overview The ORCA OR3LxxxB FPGAs are a new generation of SRAM-based FPGAs built on the ...

Page 6

ORCA OR3LxxxB Series FPGAs Description (continued) F5D K7_0 K7_1 K7_2 K7_3 K6_0 K6_1 K6_2 K6_3 K5_0 K5_1 K5_2 K5_3 K4_0 K4_1 K4_2 K4_3 F5C CLK SEL CIN CE 1 ASWE LSR 0 F5B K3_0 K3_1 K3_2 K3_3 K2_0 K2_1 K2_2 ...

Page 7

Data Addendum March 2002 Description (continued) 0/1 DEC 0/1 Lattice Semiconductor BRI9 BL09 I9 BR09 BLI9 BRI8 BL08 I8 BR08 BLI8 BRI7 BL07 I7 BR07 BLI7 BRI6 BL06 I6 BR06 BLI6 BRI5 BL05 I5 BR05 BLI5 BRI4 BL04 I4 BR04 ...

Page 8

ORCA OR3LxxxB Series FPGAs Description (continued) PIC Logic The OR3LxxxB PIC addresses the demand for ever- increasing system clock speeds. Each PIC contains four programmable inputs/outputs (PIOs) and routing resources. On the input side, each PIO contains a fast- capture ...

Page 9

Data Addendum March 2002 Description (continued) System Features The OR3LxxxB Series also provides system-level func- tionality by means of its dual-use MPI and its innovative PCM. These functional blocks allow for easy glueless system interfacing and the capability to adjust ...

Page 10

ORCA OR3LxxxB Series FPGAs Description (continued) Series 3L I/Os and 5 V Tolerance Series 3L devices use the same I/O structure as ORCA Series 3T devices. ORCA Series 3L devices use a 3.3 V supply ( power the ...

Page 11

Data Addendum March 2002 Description (continued) ORCA Foundry Development System The ORCA Foundry development system is used to process a design from a netlist to a configured FPGA. This system is used to map a design onto the ORCA architecture ...

Page 12

... PRGM Pulse Width Low to Start Reconfiguration PGW Master and Asynchronous Peripheral Modes T Power-on Reset Delay PO T CCLK Period ( CCLK ( Configuration Latency (autoincrement mode): CL OR3L165B ( ( OR3L225B ( ( Microprocessor (MPI) Mode T Power-on Reset Delay PO T Configuration Latency (autoincrement mode): CL OR3L165B OR3L225B T Partial Reconfi ...

Page 13

Data Addendum March 2002 Timing Characteristics (continued) In addition to supply voltage, process variation, and operating temperature, circuit and process improve- ments of the ORCA Series FPGAs over time will result in significant improvement of the actual performance over those ...

Page 14

ORCA OR3LxxxB Series FPGAs Timing Characteristics (continued) Table 6. Sequential PFU Timing Characteristics OR3LxxB Commercial 2.63 V, –40 °C DD Symbol Input ...

Page 15

Data Addendum March 2002 Timing Characteristics (continued) Table 7. Ripple Mode PFU Timing Characteristics OR3LxxB Commercial 2.63 V, –40 °C DD Symbol ...

Page 16

ORCA OR3LxxxB Series FPGAs Timing Characteristics (continued) Table 7. Ripple Mode PFU Timing Characteristics (continued) OR3LxxB Commercial 2.63 V, –40 °C DD ...

Page 17

Data Addendum March 2002 Timing Characteristics (continued) Table 8. Synchronous Memory Write Characteristics OR3LxxB Commercial 2.63 V, –40 °C DD Symbol Write ...

Page 18

ORCA OR3LxxxB Series FPGAs Timing Characteristics (continued) Table 9. Synchronous Memory Read Characteristics OR3LxxB Commercial 2.63 V, –40 °C DD Symbol (T ...

Page 19

Data Addendum March 2002 Timing Characteristics (continued) PLC Timing Table 10. PFU Output MUX and Direct Routing Timing Characteristics OR3LxxB Commercial 2.63 ...

Page 20

ORCA OR3LxxxB Series FPGAs Timing Characteristics (continued) PIO Timing. Table 12. Programmable I/O Timing Characteristics OR3LxxB Commercial 2.63 V, –40 °C DD ...

Page 21

Data Addendum March 2002 Timing Characteristics (continued) Table 12. Programmable I/O Timing Characteristics (continued) OR3LxxB Commercial 2.63 V, –40 °C DD Symbol ...

Page 22

ORCA OR3LxxxB Series FPGAs Timing Characteristics (continued) Table 12. Programmable I/O Timing Characteristics (continued) OR3LxxB Commercial 2.63 V, –40 °C DD Symbol ...

Page 23

Data Addendum March 2002 Timing Characteristics (continued) Special Function Blocks Timing Table 13. Microprocessor Interface (MP I) Timing Characteristics OR3LxxB Commercial 2.63 ...

Page 24

ORCA OR3LxxxB Series FPGAs Timing Characteristics (continued) Table 13. Microprocessor Interface (MP I) Timing Characteristics (continued) OR3LxxB Commercial 2.63 V, –40 °C ...

Page 25

Data Addendum March 2002 Timing Characteristics (continued) Clock Timing Table 14. ExpressCLK (ECLK) and Fast Clock (FCLK) Timing Characteristics OR3LxxB Commercial 2.63 ...

Page 26

ORCA OR3LxxxB Series FPGAs Timing Characteristics (continued) Table 15. General-Purpose Clock Timing Characteristics (Internally Generated Clock) OR3LxxB Commercial 2.63 V, –40 °C ...

Page 27

Data Addendum March 2002 Timing Characteristics (continued) Table 16. OR3Lxxx ExpressCLK to Output Delay (Pin-to-Pin) OR3LxxB Commercial 2.63 V, –40 °C DD ...

Page 28

ORCA OR3LxxxB Series FPGAs Timing Characteristics (continued) Table 17. OR3Lxxx Fast Clock (FCLK) to Output Delay (Pin-to-Pin) OR3LxxB Commercial 2.63 V, –40 ...

Page 29

Data Addendum March 2002 Timing Characteristics (continued) Table 18. OR3Lxxx General System Clock (SCLK) to Output Delay (Pin-to-Pin) OR3LxxB Commercial 2.63 V, ...

Page 30

ORCA OR3LxxxB Series FPGAs Timing Characteristics (continued) Table 19. OR3Lxxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin) OR3LxxB Commercial 2.63 V, ...

Page 31

Data Addendum March 2002 Timing Characteristics (continued) Table 19. OR3Lxxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin) (continued) OR3LxxB Commercial 2.63 ...

Page 32

ORCA OR3LxxxB Series FPGAs Timing Characteristics (continued) Table 20. OR3Lxxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) OR3LxxB Commercial 2.63 V, –40 ...

Page 33

Data Addendum March 2002 Timing Characteristics (continued) Table 20. OR3Lxxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) (continued) OR3LxxB Commercial 2.63 V, ...

Page 34

ORCA OR3LxxxB Series FPGAs Timing Characteristics (continued) Table 21. OR3Lxxx Input to General System Clock (SCLK) Setup/Hold Time (Pin-to-Pin) OR3LxxB Commercial 2.63 ...

Page 35

Data Addendum March 2002 Timing Characteristics (continued) Description To define speed grades, the ORCA Series part number designation (see Ordering Information) uses a single- digit number to designate a speed grade. This number is not related to any single ac ...

Page 36

ORCA OR3LxxxB Series FPGAs Timing Characteristics (continued) Table 22. Derating for Commercial/Industrial OR3Lxxx Devices (I/O Supply V Power Supply Voltage T J (°C) 3.0 V 3.3 V –40 0.82 0.72 0 0.91 0.80 25 0.98 0.85 85 1.00 0.99 100 ...

Page 37

... Lattice Semiconductor OR3L165B Clock Power P = [0.039 mW/MHz + (0.046 mW/MHz/Branch) (# Branches) + (0.008 mW/MHz/PFU) (# PFUs) + (0.002 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3L165B clock power = 9.8 mW/MHz OR3L225B Clock Power PIC P = [0.045 mW/MHz + (0.053 mW/MHz/Branch) (# Branches) + (0.008 mW/MHz/PFU) (# PFUs) + (0.002 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3L225B clock power = 13 ...

Page 38

... DD 29 PL18C 30 PL18A I/O-A8/MPI_RW PL19D I/O-A9/MPI_ACK 33 PL19A 34 PL20D 35 PL20A I/O-A10/MPI_BI 36 PL21D 37 PL21A 38 PL22D 39 PL22A I/O-A11/MPI_IRQ PL23D 42 PL23B 38 Function Pin OR3L165B V 43 PL24D PL24B SS I/O 45 PL25D 46 PL27A PL29D DD I/O 48 PL30D 49 PL30A I/O-A2 50 PL32A I/O 51 I/O 52 PCCLK I/O- I/O ...

Page 39

... PR22A 118 PR22D 119 PR21A 120 PR21D 121 PR20A 122 PR20D 123 PR19A 124 PR19D 125 V SS 126 PR18A Lattice Semiconductor Function Pin OR3L165B V 2 127 PR18D DD I/O 128 PR17B I/O 129 PR17D I/O 130 I/O-HDC 131 PECKR I/O 132 PR16D I/O 133 PR15B I/O 134 ...

Page 40

... PECKT 179 PT18B 180 PT17D 181 PT17A 182 V SS 183 PT16D 184 PT16C 185 186 PT15A 187 V SS 188 PT14D 40 Function Pin OR3L165B I/O 189 PT14A I/O 190 PT13D I/O 191 PT13A I/O-D5 192 PT12D I/O 193 PT12A I/O 194 PT11D I/O 195 PT11A I/O-D4 196 V 197 PT10D SS ...

Page 41

... I/O-A7/MPI_CLK PL17D PL18C 34 PL18A I/O-A8/MPI_RW PL19D I/O-A9/MPI_ACK 37 PL19A 38 PL20D 39 PL20A I/O-A10/MPI_BI 40 PL21D 41 PL21A Lattice Semiconductor Function Pin OR3L165B V 42 PL22D PL22A DD I/O 44 I/O 45 PL23D I/O 46 PL23B 47 PL24D V 48 PL24B PL24A DD I/O 50 PL25D I/O 51 PL26D 52 PL27A ...

Page 42

... PB29A 115 PB30A 116 PB30D 117 PB32D 118 V SS 119 PDONE 120 V DD 121 V SS 122 PRESETN 123 PPRGMN 124 PR32A 42 Function Pin OR3L165B I/O 125 PR31D I/O 126 PR30A V 127 PR29A SS I/O 128 I/O 129 PR28A I/O 130 PR27A I/O 131 PR26A V 132 PR26D SS I/O-ECKB 133 ...

Page 43

... DD 194 PT25D 195 PT24D 196 PT23D 197 V DD 198 PT22D 199 PT22A 200 PT21D 201 PT21A 202 PT20D 203 PT20A Lattice Semiconductor Pin OR3L165B Function 204 PT19D I/O I/O 205 PT19A I/O 206 207 PECKT I/O 208 PT18B 209 PT17D I/O I/O 210 PT17A V 211 SS 212 ...

Page 44

... I/O-A1/MPI_BE1 H2 PL9D J4 PL9C H1 PL9B H3 PL9A J2 PL10D J1 PL10C K2 PL10B J3 PL10A K1 PL11D K4 PL11A L2 PL12D K3 PL12A L1 PL13D M2 PL13A M1 PL14D L3 PL14A N2 PECKL M4 PL15A N1 PL16C M3 PL16A I/O-A7/MPI_CLK 44 Function Pin OR3L165B I/O P2 PL17D I/O P4 I/O P1 PL18C I/O N3 PL18A R2 PL19D I/O P3 PL19A I/O R1 PL20D I/O T2 PL20A I/O R3 PL21D PL21A DD I/O R4 PL22D I/O U2 PL22A I/O T3 PL23D I/O U1 PL23C I/O U4 ...

Page 45

... AE11 PB12A AD10 PB12D AF11 PB13A AE12 PB13D AF12 PB14A AD11 PB14D AE13 PB15A AC12 PB15D AF13 PB16B AD12 PB16D Lattice Semiconductor Function Pin OR3L165B I/O-A15 AE14 PECKB CCLK AC14 PB17D I/O-A16 AF14 PB18B I/O AD13 PB18D I/O AE15 AD14 PB19D I/O I/O AF15 PB20A V 2 ...

Page 46

... PR21A T26 PR21D R25 PR20A R26 PR20D T24 PR19A P25 PR19D R23 PR18A P26 PR18D R24 PR17B N25 PR17D N23 PECKR 46 Function Pin OR3L165B N26 PR16D RESET P24 PR15B PRGM I/O-M0 M25 PR15D I/O N24 I/O M26 PR14D I/O L25 PR13A I/O M24 PR13D I/O L26 PR12A ...

Page 47

... A15 PT19D C16 PT19A B14 PECKT D15 PT18B A14 PT17D C15 PT17A B13 PT16D D13 PT16C A13 C14 PT15A Lattice Semiconductor Function Pin OR3L165B I/O B12 PT14D I/O C13 PT14A I/O A12 PT13D B11 PT13A I/O C12 PT12D I/O A11 PT12A I/O D12 PT11D I/O B10 PT11A I/O ...

Page 48

... V SS L14 V SS L15 V SS L16 V SS M11 V SS M12 V SS M13 V SS M14 V SS M15 V SS M16 Function Pin OR3L165B V N11 SS V N12 SS V N13 SS V N14 SS V N15 SS V N16 SS V P11 SS V P12 SS V P13 SS V P14 SS V ...

Page 49

... Data Addendum March 2002 Pin Information (continued) Table 27. 432-Pin EBGA Pinout Pin OR3L165B E4 PRD_CFGN D3 PR1D D2 PR1A D1 PR2D F4 PR2A E3 PR3D E2 PR3C E1 PR3B F3 PR3A F2 PR4D F1 PR4C H4 PR4B G3 PR4A G2 PR5D G1 PR5C J4 PR5B PR6A J3 PR7C K4 PR7A J2 PR8A J1 PR9D K3 PR9C K2 PR9B K1 PR9A L3 PR10D M4 PR10C ...

Page 50

... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 27. 432-Pin EBGA Pinout (continued) Pin OR3L165B R1 PR16D T2 PECKR T4 PR17D T3 PR17B U1 PR18D U2 PR18A U3 PR19D V1 PR19B V2 PR19A V3 PR20D W1 PR20A V4 PR21D W2 PR21B W3 PR21A Y2 PR22D W4 PR22A Y3 PR23D AA1 PR23C AA2 PR23B Y4 PR23A AA3 AB1 PR24C AB2 ...

Page 51

... Data Addendum March 2002 Pin Information (continued) Table 27. 432-Pin EBGA Pinout (continued) Pin OR3L165B AF4 PR31A AH1 PR32B AH2 PR32A AH3 PPRGMN AG4 PRESETN AH5 PDONE AJ4 PB32D AK4 PB32C AL4 PB31D AH6 PB31A AJ5 PB30D AK5 PB30C AL5 PB30B AJ6 ...

Page 52

... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 27. 432-Pin EBGA Pinout (continued) Pin OR3L165B AJ14 PB20B AK14 PB20A AL14 PB19D AJ15 AK15 PB18D AL15 PB18B AK16 PB17D AH16 PECKB AJ16 PB16D AL17 PB16B AK17 PB15D AJ17 PB15A AL18 PB14D AK18 ...

Page 53

... Data Addendum March 2002 Pin Information (continued) Table 27. 432-Pin EBGA Pinout (continued) Pin OR3L165B AK26 PB4B AJ26 PB4A AL27 AK27 PB3C AJ27 PB3B AH26 PB3A AL28 PB2D AK28 PB2A AJ28 PB1B AH27 PB1A AG28 PCCLK AH29 PL32A AH30 PL32B AH31 ...

Page 54

... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 27. 432-Pin EBGA Pinout (continued) Pin OR3L165B Y30 PL21A W29 PL21C W30 PL21D V28 PL20A W31 PL20C V29 PL20D V30 PL19A V31 PL19C U29 PL19D U30 PL18A U31 PL18C T30 T28 PL17D T29 ...

Page 55

... Data Addendum March 2002 Pin Information (continued) Table 27. 432-Pin EBGA Pinout (continued) Pin OR3L165B G31 PL5B G30 PL5C G29 H28 PL4A F31 PL4B F30 PL4C F29 PL4D E31 PL3A E30 PL3B E29 PL3C F28 PL3D D31 PL2A D30 PL2D D29 ...

Page 56

... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 27. 432-Pin EBGA Pinout (continued) Pin OR3L165B D20 PT9D B21 PT10A A21 PT10D C20 PT11A D19 PT11D B20 PT12A C19 PT12C B19 PT12D D18 PT13A A19 PT13C C18 PT13D B18 PT14A A18 PT14C C17 ...

Page 57

... Data Addendum March 2002 Pin Information (continued) Table 27. 432-Pin EBGA Pinout (continued) Pin OR3L165B D10 PT27A C9 PT27B B8 PT27C C8 PT27D D9 PT28A A7 PT28B B7 PT28C C7 PT28D D8 PT29A A6 PT29B B6 PT29C C6 PT29D A5 PT30A B5 PT30B C5 PT30C D6 PT30D A4 PT31A B4 PT31B C4 PT32A D5 PT32D A12 V SS A16 A20 ...

Page 58

... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 27. 432-Pin EBGA Pinout (continued) Pin OR3L165B AL2 V SS AL20 V SS AL24 V SS AL29 V SS AL3 V SS AL30 V SS AL8 B29 B31 C30 V SS C31 V SS ...

Page 59

... Data Addendum March 2002 Pin Information (continued) Table 27. 432-Pin EBGA Pinout (continued) Pin OR3L165B AL1 V DD AL31 B30 V DD C29 D11 V DD D15 V DD D17 V DD D21 V DD D25 V DD D28 G28 V DD ...

Page 60

... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 28. 680-Pin PBGAM Pinout Pin OR3L165B D1 PL1D E2 PL1C E1 PL1B F4 PL1A F3 PL2D F2 PL2A F1 PL3D G5 PL3C G4 PL3B G2 PL3A G1 PL4D H5 PL4C H4 PL4B H2 PL4A H1 PL5C J5 PL5B J4 PL5A J3 PL6D J2 PL6C J1 PL6B K5 PL6A K4 PL7D K3 PL7C K2 PL7B K1 PL7A L5 PL8D L4 PL8C L2 PL8B ...

Page 61

... Data Addendum March 2002 Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B R5 PL12A R4 PL13D R2 PL13C R1 PL13B T5 PL14D T4 PL14C T2 PL14B T1 PL14A U5 PECKL U4 PL15C U3 PL15A U2 PL16C U1 PL16A V1 PL17D V2 PL18C V3 PL18A V4 PL19D V5 PL19C W1 PL19B W2 PL19A W4 PL20D W5 PL20C Y1 PL20B Y2 PL20A Y4 PL21D Y5 PL21C AA1 ...

Page 62

... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B AD5 PL26D AE1 PL26C AE2 PL26B AE3 PL26A AE4 PL27D AE5 PL27C AF1 PL27B AF2 PL27A AF3 PL28D AF4 PL28C AF5 PL28B AG1 PL28A AG2 PL29C AG4 ...

Page 63

... Data Addendum March 2002 Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B AM9 PB6A AN9 PB6B AP9 PB6C AK10 PB6D AL10 PB7A AM10 PB7B AN10 PB7C AP10 PB7D AK11 PB8A AL11 PB8B AN11 PB8C AP11 PB8D AK12 PB9A AL12 ...

Page 64

... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B AK18 PB18D AP19 PB19B AN19 PB19C AL19 PB19D AK19 PB20A AP20 PB20B AN20 PB20C AL20 PB20D AK20 PB21A AP21 PB21B AN21 PB21C AM21 PB21D AL21 PB22A AK21 ...

Page 65

... Data Addendum March 2002 Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B AL28 PB30B AK28 PB30C AP29 PB30D AN29 PB31A AM29 PB31D AL29 PB32A AP30 PB32C AN30 PB32D AP31 PDONE AL34 PRESETN AK33 PPRGMN AK34 PR32A AJ31 PR32B AJ32 ...

Page 66

... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B AB31 PR23C AB32 PR23D AB33 PR22A AB34 PR22B AA30 PR22C AA31 PR22D AA32 PR21A AA33 PR21B AA34 PR21C Y30 PR21D Y31 PR20A Y33 PR20B Y34 PR20C W30 ...

Page 67

... Data Addendum March 2002 Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B N31 PR10D N30 PR9A M34 PR9B M33 PR9C M31 PR9D M30 PR8A L34 PR8B L33 PR8C L31 PR8D L30 PR7A K34 PR7B K33 PR7C K32 PR7D K31 ...

Page 68

... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B D28 PT30B B28 PT30A A28 PT29D E27 PT29C D27 PT29B B27 PT29A A27 PT28D E26 PT28C D26 PT28B C26 PT28A B26 PT27D A26 PT27C E25 PT27B D25 ...

Page 69

... Data Addendum March 2002 Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B E18 PT19A D18 PECKT C18 PT17D B18 PT17C A18 PT17A A17 PT16D B17 PT16C C17 PT15A D17 PT14D E17 PT14C A16 PT14B B16 PT14A D16 PT13D E16 ...

Page 70

... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B C9 PT5C D9 PT5B E9 PT5A A8 PT4D B8 PT4C D8 PT4B E8 PT4A A7 PT3D B7 PT3C D7 PT3B E7 PT3A A6 PT2D B6 PT2C C6 PT2A D6 PT1D A5 PT1C B5 PT1A A4 PRD_DATA A33 V SS A34 ...

Page 71

... Data Addendum March 2002 Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B N20 V SS N21 V SS N22 V SS P13 V SS P14 V SS P15 V SS P20 V SS P21 V SS P22 V SS R13 V SS R14 V SS R15 V SS R20 V SS R21 ...

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... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B AA15 V SS AA20 V SS AA21 V SS AA22 V SS AB13 V SS AB14 V SS AB15 V SS AB20 V SS AB21 V SS AB22 V SS AC3 V SS AC32 V SS AG3 V SS AG32 ...

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... Data Addendum March 2002 Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B E32 F30 N16 N17 N18 N19 P16 P17 P18 P19 R16 R17 R18 ...

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... ORCA OR3LxxxB Series FPGAs Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B AA16 AA17 AA18 AA19 AB16 AB17 AB18 AB19 AJ5 AJ30 AK3 AK4 AK5 AK6 ...

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... Data Addendum March 2002 Pin Information (continued) Table 28. 680-Pin PBGAM Pinout (continued) Pin OR3L165B D33 G32 L32 R32 Y32 V DD AD3 V DD AD32 V DD AH3 V DD AH32 V DD AL2 V DD AL3 V DD AL32 ...

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ORCA OR3LxxxB Series FPGAs Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or ...

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... V Standby Current DDSB OR3L165B internal oscillator stopped, no output loads, OR3L225B inputs V Powerup Current: I Power supply current at approximately OR3L165B within a recommended power supply ramp OR3L225B rate of 1 ms—200 ms Input Capacitance Test frequency = 1 MHz Output Capacitance C T OUT ...

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ORCA OR3LxxxB Series FPGAs Package Thermal Characteristics There are four thermal parameters that are in common ψ use: Θ should be noted that all Θ Θ JA, JC, JC, and JB the parameters are affected, to varying degrees, ...

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Data Addendum March 2002 Package Thermal Characteristics FPGA Maximum Junction Temperature Once the power dissipated by the FPGA has been determined (see the Estimating Power Dissipation section), the maximum junction temperature of the FPGA can be found. This is needed ...

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ORCA OR3LxxxB Series FPGAs Package Coplanarity The coplanarity limits of the ORCA Series 3 packages are as follows. Table 33. Package Coplanarity Coplanarity Limit Package Type EBGA PBGA SQFP2 PBGAM1 Package Parasitics The electrical performance package, such ...

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Data Addendum March 2002 Package Outline Diagrams Terms and Definitions Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. ...

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ORCA OR3LxxxB Series FPGAs Package Outline Diagrams 208-Pin SQFP2 Dimensions are in millimeters. 30.60 ± 0.20 28.00 ± 0.20 21.0 REF PIN #1 IDENTIFIER ZONE 208 53 EXPOSED HEAT SINK APPEARS ON BOTTOM SURFACE: CHIP BONDED FACE UP. (SEE DETAIL ...

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Data Addendum March 2002 Package Outline Diagrams 240-Pin SQFP2 Dimensions are in millimeters. 34.60 ± 0.20 32.00 ± 0.20 24.2 REF PIN #1 IDENTIFIER ZONE 240 EXPOSED HEAT SINK APPEARS ON BOTTOM SURFACE: CHIP BONDED FACE UP. ...

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ORCA OR3LxxxB Series FPGAs Package Outline Diagrams 352-Pin PBGA Dimensions are in millimeters. A1 BALL IDENTIFIER ZONE MOLD COMPOUND PWB 0.56 ± 0.06 0.60 ± 0. CENTER ARRAY G FOR THERMAL ENHANCEMENT ...

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Data Addendum March 2002 Package Outline Diagrams 432-Pin EBGA Dimensions are in millimeters. A1 BALL IDENTIFIER ZONE 0.91 ± 0.06 0.63 ± 0. BALL ...

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ORCA OR3LxxxB Series FPGAs Package Outline Diagrams 680-Pin PBGAM Dimensions are in millimeters. A1 BALL IDENTIFIER ZONE 0.61 ± 0.08 0.50 ± 0. ...

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... PS = Power Quad Shrink Flat Package (SQFP2) Table 35. Voltage Options Device OR3LxxxB 2.5 V internal/3.3 V I/O Table 36. Ordering Information Device Family Part Number OR3L165B OR3L165B8PS208-DB OR3L165B8PS240-DB OR3L165B8BA352-DB OR3L165B8BC432-DB OR3L165B8BM680-DB OR3L165B7PS208-DB OR3L165B7PS240-DB OR3L165B7BA352-DB OR3L165B7BC432-DB OR3L165B7BM680-DB OR3L225B OR3L225B8BC432-DB OR3L225B8BM680-DB OR3L225B7BC432-DB OR3L225B7BM680-DB Lattice Semiconductor OR3LXXXB X XX XXX X Voltage ...

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... Device Family Part Number OR3L165B OR3L165B7PS208I-DB OR3L165B7PS240I-DB OR3L165B7BA352I-DB OR3L165B7BC432I-DB OR3L165B7BM680I-DB OR3L225B OR3L225B7BC432I-DB OR3L225B7BM680I-DB www.latticesemi.com Copyright © 2002 Lattice Semiconductor All Rights Reserved March 2002 DA99-011FPGA (Replaces DA99-008FPGA and must accompany DS99-087FPGA) Industrial Speed Package Pin/Ball Grade Type Count 7 SQFP2 208 7 SQFP2 ...

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