or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 5

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

Data Addendum
March 2002
Lattice Semiconductor
Support
Description
FPGA Overview
The ORCA OR3LxxxB FPGAs are a new generation of
SRAM-based FPGAs built on the successful Series 2
and Series 3 FPGA lines, with enhancements and
innovations geared toward today’s high-speed designs
and tomorrow’s systems on a single chip. Designed
from the start to be synthesis friendly and to reduce
place and route times while maintaining the complete
routability of the ORCA Series 2 devices, the
OR3LxxxB Series more than doubles the logic avail-
able in each logic block and incorporates system-level
features that can further reduce logic requirements and
increase system speed. ORCA OR3LxxxB devices
contain many new patented enhancements and are
offered in a variety of packages, speed grades, and
temperature ranges.
The ORCA OR3LxxxB Series FPGAs consist of three
basic elements: PLCs, programmable input/output
cells (PICs), and system-level features. An array of
PLCs is surrounded by PICs. Each PLC contains a
PFU, a SLIC, local routing resources, and configuration
RAM. Most of the FPGA logic is performed in the PFU
(see Figure 1), but decoders, PAL -like functions, and
3-state buffering can be performed in the SLIC (see
Figure 2). The PICs provide device inputs and outputs
and can be used to register signals and to perform
input demultiplexing, output multiplexing, and other
functions on two output signals (see Figure 3). Some of
the system-level functions include the MPI and the
PCM.
ORCA Foundry development system support.
Supported by industry-standard CAE tools for design
entry, synthesis, simulation, and timing analysis.
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit)
LUTs, eight latches/FFs, and one additional FF that
may be used independently or with arithmetic func-
tions.
The PFU is organized in a twin-quad fashion: two sets
of four LUTs and FFs that can be controlled indepen-
dently. LUTs may also be combined for use in arith-
metic functions using fast-carry chain logic in either
4-bit or 8-bit modes. The carry-out of either mode may
be registered in the ninth FF for pipelining. Each PFU
may also be configured as a synchronous 32
gle- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from
invertible PFU inputs, or they can be tied high or tied
low. The FFs also have programmable clock polarity,
clock enables, and local set/reset.
The SLIC is connected to PLC routing resources and to
the outputs of the PFU. It contains 3-state, bidirectional
buffers and logic to perform up to a 10-bit AND function
for decoding, or an AND-OR with optional INVERT to
perform PAL -like functions. The 3-state drivers in the
SLIC and their direct connections to the PFU outputs
make fast, true 3-state buses possible within the
FPGA, reducing required routing and allowing for real-
world system performance.
ORCA OR3LxxxB Series FPGAs
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