or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 35

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

Data Addendum
March 2002
Lattice Semiconductor
Timing Characteristics
Description
To define speed grades, the ORCA Series part number
designation (see Ordering Information) uses a single-
digit number to designate a speed grade. This number
is not related to any single ac parameter. Higher num-
bers indicate a faster set of timing parameters. The
actual speed sorting is based on testing the delay in a
path consisting of an input buffer, combinatorial delay
through all PLCs in a row, and an output buffer. Other
tests are then done to verify other delay parameters,
such as routing delays, setup times to FFs, etc.
The most accurate timing characteristics are reported
by the timing analyzer in the ORCA Foundry Develop-
ment System. A timing report provided by the develop-
ment system after layout divides path delays into logic
and routing delays. The timing analyzer can also pro-
vide logic delays prior to layout. While this allows rout-
ing budget estimates, there is wide variance in routing
delays associated with different layouts.
The logic timing parameters noted in the Electrical
Characteristics section of this data sheet are the same
as those in the design tools. In the PFU timing, symbol
names are generally a concatenation of the PFU oper-
ating mode and the parameter type. The setup, hold,
and propagation delay parameters, defined below, are
designated in the symbol name by the SET, HLD, and
DEL characters, respectively.
(continued)
The values given for the parameters are the same as
those used during production testing and speed bin-
ning of the devices. The junction temperature and sup-
ply voltage used to characterize the devices are listed
in the delay tables. Actual delays at nominal tempera-
ture and voltage for best-case processes can be much
better than the values given.
It should be noted that the junction temperature used in
the tables is generally 85 °C. The junction temperature
for the FPGA depends on the power dissipated by the
device, the package thermal characteristics (Θ
the ambient temperature, as calculated in the following
equation and as discussed further in the Package
Thermal Characteristics section:
Note: The user must determine this junction tempera-
Table 22 and Table 23 provide approximate power sup-
ply and junction temperature derating for OR3Lxxx
commercial and industrial devices. The delay values in
this data sheet and reported by ORCA Foundry are
shown as 1.00 in the tables. The method for determin-
ing the maximum junction temperature is defined in the
Package Thermal Characteristics section. Taken cumu-
latively, the range of parameter values for best-case vs.
worst-case processing, supply voltage, and junction
temperature can approach three to one.
ture to see if the delays from ORCA Foundry
should be derated based on the following derat-
ing tables.
ORCA OR3LxxxB Series FPGAs
T
Jmax =
T
Amax
+ (P • Θ
JA
) °C
JA
), and
35