or3l165b Lattice Semiconductor Corp., or3l165b Datasheet - Page 4

• Manufacturer Part Number: or3l165b
• Description: Orca Or3lxxxb Series Field-programmable Gate Arrays
• Manufacturer: Lattice Semiconductor Corp.

ORCA OR3LxxxB Series FPGAs
Features
System-Level Features
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the ORCA OR3LxxxB include the following:
Table 2 . ORCA Series 3L System Performance
1. Implemented using 8
2. Implemented using two 32
3. Implemented using 8
4. Implemented using 32
5. Implemented using 32
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
4 4
16-bit Loadable Up/Down Counter
16-bit Accumulator
8 × 8 Parallel Multiplier:
32 × 16 RAM (synchronous):
128 × 8 RAM (synchronous):
8-bit Address Decode (internal):
32-bit Address Decode (internal):
36-bit Parity Check (internal)
only pipelining registers).
Programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF)/
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and PAL-like
— Output FF and two-signal function generator to
— Fast open-drain drive capability.
New programmable I/O 3-state FF allows 3-state
buffer control signals to be set up a clock cycle early
for improved clock to output delays.
Full PCI local bus compliance for all devices in
3.3 V and 5 V PCI systems. Pin-selectable I/O
clamping diodes provide 3.3 V and 5 V compliance
and 5 V tolerance.
Multiplier Mode, Unpipelined
ROM Mode, Unpipelined
Multiplier Mode, Pipelined
Single-port, 3-state Bus
Dual-port
Single-port, 3-state Bus
Dual-port
Using Softwired LUTs
Using SLICs
Using Softwired LUTs
Using SLICs
latch for reduced input setup time and zero hold
time.
functions.
reduce CLK to output propagation delay.
5
5
(continued)
6
7
×
×
×
×
Parameter
1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (seven of 15 PFUs contain
4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
4 dual-port RAM mode.
×
12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
4
4
2
3
1
# PFUs
11.5
0.25
* i960 is a registered trademark of Intel Corporation.
†
15
2
2
8
4
4
8
8
0
2
0
2
PowerPC is a registered trademark of International Business
Machines, Inc.
Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to i960 * and
PowerPC
address space provided.
Parallel readback of configuration data capability with
the built-in microprocessor interface.
Programmable clock manager (PCM) adjusts clock
phase and duty cycle for input clock rates from
5 MHz to 120 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as dig-
ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers. Two PCMs are provided
per device.
True internal 3-state, bidirectional buses with simple
control provided by the SLIC.
32
port. Create large, fast RAM/ROM blocks (128
only eight PFUs) using the SLIC decoders as bank
drivers.
Full UTOPIA Level III I/O compliance (6.0 ns
CLK -> OUT, 2.0 ns setup with 0 ns hold).
×
4 RAM per PFU, configurable as single- or dual-
2.30
1.29
7.97
3.75
7.97
151
151
129
173
231
151
151
38
93
†
-7
processors with user-configurable
2.00
1.12
6.84
3.16
6.84
176
176
116
152
209
277
181
181
46
-8
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
Lattice Semiconductor
Data Addendum
March 2002
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