mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 820

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 18 External Bus Interface (S12XEBIV4)
1. EWAIT function is enabled if at least one CSx line is configured respectively in MMCCTL0. Refer to S12X_MMC section and
820
ITHRS
Table
ASIZ[4:0]
ITHRS
0
1
HDBE
Field
4–0
7
5
18-5.
External Signal
TAGHI, TAGLO
TAGHI, TAGLO
DATA[15:8]
DATA[15:8]
DATA[7:0]
DATA[7:0]
Reduced Input Threshold — This bit selects reduced input threshold on external data bus pins and specific
control input signals which are in use with the external bus interface in order to adapt to external devices with a
3.3 V, 5 V tolerant I/O.
The reduced input threshold level takes effect depending on ITHRS, the operating mode and the related enable
signals of the EBI pin function as summarized in
0 Input threshold is at standard level on all pins
1 Reduced input threshold level enabled on pins in use with the external bus interface
High Data Byte Enable — This bit enables the higher half of the 16-bit data bus. If disabled, only the lower 8-
bit data bus can be used with the external bus interface. In this case the unused data pins and the data select
signals (UDS and LDS) are free to be used for alternative functions.
0 DATA[15:8], UDS, and LDS disabled
1 DATA[15:8], UDS, and LDS enabled
External Address Bus Size — These bits allow scalability of the external address bus. The programmed value
corresponds to the number of available low-aligned address lines (refer to
ADDR[22:0] start up as outputs after reset in expanded modes. This needs to be taken into consideration when
using alternative functions on relevant pins in applications which utilize a reduced external address bus.
EWAIT
EWAIT
ASIZ[4:0]
00000
00001
00010
00011
10110
Table 18-3. Input Threshold Levels on External Signals
:
Standard
Standard
NS
MC9S12XF - Family Reference Manual, Rev.1.19
Table 18-2. EBICTL0 Field Descriptions
Table 18-4. External Address Bus Size
Standard
Standard
SS
Available External Address Lines
ADDR[21:1], UDS
Description
Table
ADDR[2:1], UDS
if HDBE = 1
enabled
Standard
Reduced
Reduced
Reduced
if EWAIT
ADDR1, UDS
NX
None
18-3.
UDS
:
(1)
Reduced
Standard
Reduced
Standard
ES
Table
18-4). All address lines
Reduced
Standard
Reduced
Reduced
if EWAIT
enabled
EX
Freescale Semiconductor
1
Standard
Standard
Reduced
ST