mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 1106

no-image

mc9s12xf512

Manufacturer Part Number
mc9s12xf512
Description
S12x Microcontrollers 16-bit Automotive Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc9s12xf512MLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12xf512MLM
Manufacturer:
FREESCALE
Quantity:
201
Part Number:
mc9s12xf512MLM
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12xf512MLM
Manufacturer:
FREESCALE/NXP
Quantity:
20 000
Chapter 25 Serial Peripheral Interface (S12SPIV5)
25.3.2.4
Read: Anytime
Write: Has no effect
1106
Module Base +0x0003
Reset
SPTEF
MODF
Field
SPIF
7
5
4
W
R
1. Data in SPIDRH is lost in this case.
2. SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read
XFRW Bit
SPIF
SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For
information about clearing SPIF Flag, please refer to
0 Transfer not yet complete.
1 New data copied to SPIDR.
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For
information about clearing this bit and placing data into the transmit data register, please refer to
0 SPI data register not empty.
1 SPI data register empty.
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 25.3.2.2, “SPI Control Register 2
register (with MODF set) followed by a write to the SPI control register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
of SPIDRL after reading SPISR with SPIF == 1.
SPI Status Register (SPISR)
0
7
0
1
= Unimplemented or Reserved
Read SPISR with SPIF == 1
Read SPISR with SPIF == 1
0
0
6
Table 25-8. SPIF Interrupt Flag Clearing Sequence
MC9S12XF - Family Reference Manual, Rev.1.19
Figure 25-6. SPI Status Register (SPISR)
Table 25-7. SPISR Field Descriptions
SPTEF
1
5
SPIF Interrupt Flag Clearing Sequence
(SPICR2)”. The flag is cleared automatically by a read of the SPI status
MODF
then
then
0
4
Description
Byte Read SPIDRH
Table
Word Read (SPIDRH:SPIDRL)
25-8.
0
0
3
Byte Read SPIDRL
Read SPIDRL
(2)
or
or
0
0
2
Byte Read SPIDRL
(1)
Freescale Semiconductor
0
0
1
Table
25-9.
0
0
0

Related parts for mc9s12xf512