mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 500

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 13 FlexRay Communication Controller (FLEXRAY)
13.5.2.29 Offset Correction Value Register (OFCORVR)
This register provides the sign extended offset correction value in microticks as it was calculated by the
clock synchronization algorithm. The FlexRay block updates this register during the NIT.
13.5.2.30 Combined Interrupt Flag Register (CIFRR)
500
Module Base + 0x003A
Module Base + 0x003C
Reset
Reset
RATECORR
OFFSET-
CORR
W
W
Field
Field
15–0
R
15–0
R
15
15
0
0
0
Rate Correction Value — protocol related variable:
correction)
This field provides the sign extended rate correction value in microticks as it was calculated by the clock
synchronization algorithm. The value is represented in 2’s complement format. This value does not include the
value limitation and the application of the external rate correction. If the magnitude of the internally calculated
rate correction value exceeds the limit given by rate_correction_out in the
(PCR13), the clock correction reached limit interrupt flag CCL_IF is set in the
(PIFR0).
Note: If the FlexRay block was not able to calculate a new rate correction term due to a lack of synchronization
Offset Correction Value — protocol related variable:
offset correction)
This field provides the sign extended offset correction value in microticks as it was calculated by the clock
synchronization algorithm. The value is represented in 2’s complement format. This value does not include the
value limitation and the application of the external offset correction. If the magnitude of the internally calculated
rate correction value exceeds the limit given by offset_correction_out field in the
29
0
Note: If the FlexRay block was not able to calculate an new offset correction term due to a lack of
14
14
0
(PIFR0).
0
0
(PCR29), the clock correction reached limit interrupt flag CCL_IF is set in the
frames, the RATECORR value is not updated.
synchronization frames, the OFFSETCORR value is not updated.
13
13
0
0
0
Figure 13-29. Offset Correction Value Register (OFCORVR)
Figure 13-30. Combined Interrupt Flag Register (CIFRR)
12
12
0
0
0
MC9S12XF - Family Reference Manual, Rev.1.19
Table 13-35. RTCORVR Field Descriptions
Table 13-36. OFCORVR Field Descriptions
11
11
0
0
0
Additional Reset: RUN Command
10
10
0
0
0
0
0
0
9
9
OFFSETCORR
0
0
0
8
8
Description
Description
vRateCorrection
MIF
vOffsetCorrection
0
0
7
7
PRIF CHIF
6
0
6
0
0
0
(before value limitation and external rate
5
5
(before value limitation and external
Protocol Configuration Register 13
WUP
IF
Protocol Interrupt Flag Register 0
0
0
4
4
Protocol Configuration Register
Protocol Interrupt Flag Register
FNEB
IF
0
0
3
3
Freescale Semiconductor
FNEA
IF
0
0
2
2
RBIF
1
0
1
0
TBIF
0
0
0
0