mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 813

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

17.4.1.2
As mentioned in the bit description of the Access Error Flag (AEF) in the MPUFLG register
there is an additional memory range implicitly defined only while the AEF bit is set: The CPU in
supervisor state can read from and write to the peripheral register space even if there is no memory
protection descriptor explicitly allowing this. This is to prevent the case that the CPU cannot clear the AEF
bit if the registers are write protected for the CPU in supervisor state.
The register address space containing the PAGE registers (EPAGE, RPAGE, GPAGE, PPAGE) at 0x0010−
0x0017 gets special treatment. It is defined like this:
17.4.1.3
Some bus-masters (CPU, XGATE) do a pre-fetch of program-code past the current instruction. The
S12XCPU pre-fetches two words past the current instruction, the XGATE pre-fetches one word, even if
the pre-fetched code is not executed. The MPU module has no way of knowing this at the time when the
pre-fetch cycles occur. Therefore this will result in an access violation if the op-code pre-fetch accesses a
memory range marked as “No-Execute” (NEX=1). This must be taken into account when defining memory
ranges with the NEX bit set adjacent to memory used for program code. The best way to do this would be
to leave some fill-bytes between the memory ranges in this case, i.e. do not set the upper memory boundary
to the address of the last op-code but to a following address which is at least two words (four bytes) away.
17.4.2
This section describes all interrupts originated by the MPU.
17.4.2.1
The MPU generates one interrupt request. It cannot be masked locally in the MPU and is meant to be used
as the source of a non-maskable hardware interrupt request for the S12X CPU.
17.4.2.2
An S12X CPU access error interrupt request is generated if the MPU has detected an illegal memory access
originating from the S12X CPU. This is a non-maskable hardware interrupt. Due to the non-maskable
nature of this interrupt, the de-assertion of this interrupt request is coupled to the S12X CPU interrupt
vector fetch instead of the local access error flag (AEF). This means leaving the access error flag (AEF) in
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The S12X CPU can always read and write these registers, regardless of the configuration in the
descriptors.
XGATE or Master3 (if available) are never allowed to read or write these registers, even if the
descriptor configuration allows accesses for other masters than the S12X CPU.
Interrupts
Implicitly defined memory descriptors
Op-code pre-fetch cycles and the NEX bit
Description of Interrupt Operation
CPU Access Error Interrupt
S12X CPU access error interrupt (AEF)
MC9S12XF - Family Reference Manual, Rev.1.19
Interrupt Source
Table 17-15. Interrupt vectors
CCR Mask Local Enable
−
Chapter 17 Memory Protection Unit (S12XMPUV2)
−
(Table
17-3),
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