mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 807

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

17.3.1.4
Read: Anytime
Write: Never
17.3.1.5
Read: Anytime
Write: Anytime
Freescale Semiconductor
Address: Module Base + 0x0003
Address: Module Base + 0x0005
ADDR[7:0]
SEL[3:0]
Reset
Reset
SVSEN
Field
Field
7–0
3–0
7
W
W
R
R
SVSEN
MPU Address Status Register 2 (MPUASTAT2)
MPU Descriptor Select Register (MPUSEL)
Access violation address bits — The ADDR[7:0] bits contain bits [7:0] of the global address which caused
the current access violation interrupt. These bits are undefined if the access error flag bit (AEF) in the MPUFLG
register is not set.
MPU supervisor state enable bit — This bit enables the memory protection for the CPU in supervisor state.
If this bit is cleared, the MPU does not affect any accesses coming from the CPU in supervisor state. This is to
prevent the CPU from locking out itself while configuring the protection descriptors (during initialization after a
system reset and during the update of the protection descriptors for a task switch). The memory protection
functionality for the other bus-masters is unaffected by this bit.
0 MPU is disabled for the CPU in supervisor state
1 MPU is enabled for the CPU in supervisor state
Descriptor select bits — The SEL[3:0] bits select which descriptor is visible in the MPU Descriptor Register
window (MPUDESC0—MPUDESC5). How many of the SEL[3:0] bits are writeable depends on the number of
implemented descriptors. The number of implemented descriptors is a configuration option defined at SoC
level. Please refer to the MCU toplevel chapter for details.
0
0
7
7
Figure 17-6. MPU Address Status Register (MPUASTAT2)
Figure 17-7. MPU Descriptor Select Register (MPUSEL)
0
0
0
6
6
MC9S12XF - Family Reference Manual, Rev.1.19
Table 17-6. MPUASTAT2 Field Descriptions
Table 17-7. MPUSEL Field Descriptions
0
0
0
5
5
0
0
0
4
4
ADDR[7:0]
Description
Description
0
0
3
3
Chapter 17 Memory Protection Unit (S12XMPUV2)
0
0
2
2
SEL[3:0]
0
0
1
1
0
0
0
0
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