mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 79

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

1.10
The VREGEN connection of the voltage regulator is tied internally to VDDR such that the voltage
regulator is always enabled with VDDR connected to a positive supply voltage. The device must be
configured with the internal voltage regulator enabled. Operation in conjunction with an external voltage
regulator is not supported.
The autonomous periodic interrupt clock output is mapped to PortT[5].
The API trimming register APITR is loaded on rising edge of RESET from the Flash IFR option field at
global address 0x40_00F0 bits[5:0] during the reset sequence. Currently factory programming of this IFR
range is not supported.
1.10.1
The VREG high temperature trimming register bits VREGHTTR[3:0] are loaded from the Flash IFR
option field at global address 0x40_00F0 bits[11:8] during the reset sequence. To use the high temperature
interrupt within the specified limits (T
factory programming of this IFR range is not supported. Note that the API trimming bits are also loaded
from 0x40_00F0[5:0].
The device temperature can be monitored on ADC0 channel[17].
The internal bandgap reference voltage can also be mapped to ADC0 analog input channel[17]. The
voltage regulator VSEL bit when set, maps the bandgap and, when clear, maps the temperature sensor to
ADC0 channel[17].
Read access to reserved VREG register space returns “0”. Write accesses have no effect. This device does
not support access abort of reserved VREG register space.
1.11
The BDM alternative clock corresponds to the oscillator clock.
1.12
MC9S12XF512 features a dedicated internal PLL for the FlexRay protocol engine. The IPLL hard IP and
the register map for the configuration registers is identical to the system IPLL.
The usage of an dedicated internal PLL allows to use cheaper crystal devices and to achieve lower
radiation.
1.12.1
The CGMIPLL module supplies the clock to the FlexRay controller. The FlexRay controller can only
operate according to FlexRay specification when it is supplied with stable 80MHz clock. The CGMIPLL
must be configured to provide an 80MHz clock on its output (see
using IPLL (CGMIPLL) Block Description“
Freescale Semiconductor
VREG Configuration
BDM Configuration
FlexRay IPLL (CGMIPLL) Configuration
Temperature Sensor Configuration
CGMIPLL function
MC9S12XF - Family Reference Manual, Rev.1.19
HTIA
and T
for more details) and the FlexRay controller must be
HTID
) these bits must be programmed to 0x8. Currently
Chapter 12, “Clock Generation Module
Chapter 1 MC9S12XF-Family Reference Manual
79