mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 507

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

13.5.2.39 Network Management Vector Length Register (NMVLR)
Write:
This register defines the length of the network management vector in bytes.
13.5.2.40 Timer Configuration and Control Register (TICCR)
Write: T2_CFG:
T2_REP, T1_REP, T1SP, T2SP, T1TR, T2TR: Normal Mode
This register is used to configure and control the two timers T1 and T2. For timer details, see
Section 13.6.17, “Timer
an absolute or relative timer.
Freescale Semiconductor
Module Base + 0x0058
Module Base + 0x005A
Reset
Reset
T2_CFG
T2_REP
W
NMVL
W
Field
Field
R
R
3–0
13
12
POC:config
15
15
0
0
0
0
Network Management Vector Length — protocol related variable:
This field defines the length of the Network Management Vector in bytes. Legal values are between 0 and 12.
Timer T2 Configuration — This bit configures the timebase mode of Timer T2.
0 T2 is absolute timer.
1 T2 is relative timer.
Timer T2 Repetitive Mode — This bit configures the repetition mode of Timer T2.
0 T2 is non repetitive
1 T2 is repetitive
14
14
0
0
0
0
POC:config
Table 13-46. Mapping of NMVRn to the Received Payload Bytes NMVn
Figure 13-39. Network Management Vector Length Register (NMVLR)
CFG
T2_
13
13
0
0
0
Figure 13-40. Timer Configuration and Control Register (TICCR)
Support”. The Timer T1 is an absolute timer. The Timer T2 can be configured as
NMVR5[NMVP[15:8]]
NMVR5[NMVP[7:0]]
REP
T2_
NMVRn Register
12
12
0
0
0
Table 13-48. TICCR Field Descriptions (Sheet 1 of 2)
MC9S12XF - Family Reference Manual, Rev.1.19
11
11
0
0
Table 13-47. NMVLR Field Descriptions
0
0
T2SP T2TR
10
10
0
0
0
0
0
0
0
0
9
9
T2ST
0
0
0
8
8
Description
Description
0
0
0
0
7
7
Chapter 13 FlexRay Communication Controller (FLEXRAY)
NMVn Received Payload
6
0
0
6
0
0
NMV10
NMV11
gNetworkManagementVectorLength
0
0
0
0
5
5
REP
T1_
0
0
0
4
4
0
0
0
3
3
T1SP T1TR
0
0
0
2
2
NMVL
0
1
0
1
0
T1ST
0
0
0
0
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