mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 405

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

11.1.3
The S12X architecture implements a number of memory mapping schemes including
The MMC module performs translation of the different memory mapping schemes to the specific global
(physical) memory implementation.
11.1.4
This subsection lists and briefly describes all operating modes supported by the MMC.
11.1.4.1
1. Resources are also called targets.
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Bus arbitration between the masters CPU, BDM, FLEXRAY and XGATE
Simultaneous accesses to different resources
1)
Resolution of target bus access collision
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU, BDM, FLEXRAY and XGATE
ROM control bits to enable the on-chip FLASH or ROM selection
Port replacement registers access control
Generation of system reset when CPU accesses an unimplemented address (i.e., an address which
does not belong to any of the on-chip modules) in single-chip modes
a CPU 8MB global map, defined using a global page (GPAGE) register and dedicated 23-bit
address load/store instructions.
a BDM 8MB global map, defined using a global page (BDMGPR) register and dedicated 23-bit
address load/store instructions.
a FLEXRAY 8 MByte global map.
a (CPU or BDM) 64KB local map, defined using specific resource page (RPAGE, EPAGE and
PPAGE) registers and the default instruction set. The 64KB visible at any instant can be considered
as the local map accessed by the 16-bit (CPU or BDM) address.
The XGATE 64 Kbyte local map.
Run mode
MMC is functional during normal run mode.
Wait mode
MMC is functional during wait mode.
Stop mode
MMC is inactive during stop mode.
S12X Memory Mapping
Modes of Operation
Power Saving Modes
MC9S12XF - Family Reference Manual, Rev.1.19
Chapter 11 Memory Mapping Control (S12XMMCV4) SUPPORTING FLEXRAY
1
(internal, external, and peripherals) (see
Figure 11-
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