mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 812

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 17 Memory Protection Unit (S12XMPUV2)
The descriptors are banked in the MPU register map.
Each descriptor can be selected for modifying using the SEL bits in the MPU Descriptor Select (MPUSEL)
register.
Table 17-14
descriptors.
The minimum granularity of each descriptor is 8 bytes. This means the protection comparators in the MPU
module cover only address bits [22:3] of each access. The lower address bits (default [2:0], depending on
descriptor granularity) are ignored.
17.4.1.1
If the memory ranges of two protection descriptors defined for the same bus-master overlap, the access
restrictions for the overlapped memory range are accumulated. For example:
812
•
•
•
a memory protection descriptor defines memory range 0x40_0000−0x41_FFFF as WP=1, NEX=0
(read and execute)
another descriptor defines memory range 0x41_0000−0x43_FFFF as WP=0, NEX=1 (read and
write)
the resulting access rights for the overlapping range 0x41_0000−0x41_FFFF are WP=1, NEX=1
(read only)
gives an overview of the types of accesses that can be configured using the protection
Overlapping Descriptors
A mis-aligned word access to the upper boundary address of a descriptor is
always flagged as an access violation.
Configuring the lower boundary address of a descriptor to be higher than the
upper boundary address of a descriptor causes this descriptor to be ignored
by the comparator block. This effectively disables the descriptor.
Avoid changing descriptors while they are in active use to validate accesses
from bus-masters. This can be done by temporarily disabling the affected
master during the update (XGATE, Master 3, switch S12X CPU states).
Otherwise accesses from bus-masters affected by a descriptor which is
updated concurrently could yield undefined results.
MC9S12XF - Family Reference Manual, Rev.1.19
WP
0
0
1
1
Table 17-14. Access Types
NEX
0
1
0
1
NOTE
NOTE
NOTE
read, write and execute
read and execute
read, write
read only
Meaning
Freescale Semiconductor