mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 245

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

8.3.2.9.1
The general guideline is that P-Flash protection can only be added and not removed.
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
8.3.2.10
The EPROT register defines which buffer RAM EEE partition areas are protected against writes.
All bits in the EPROT register are readable and writable except for RNV[6:4] which are only readable. The
EPOPEN and EPDIS bits can only be written to the protected state. The EPS bits can be written anytime
until the EPDIS bit is cleared. If the EPOPEN bit is cleared, the state of the EPDIS and EPS bits is
irrelevant.
During the reset sequence, the EPROT register is loaded from the EEE protection byte in the Flash
configuration field at global address 0x7F_FF0D located in P-Flash memory (see
by reset condition F in
sequence, the P-Flash sector containing the EEE protection byte must be unprotected, then the EEE
protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase
Freescale Semiconductor
Offset Module Base + 0x0009
Reset
W
R
EPOPEN
EEE Protection Register (EPROT)
F
7
P-Flash Protection Restrictions
1. Allowed transitions marked with X, see
Protection
Scenario
From
= Unimplemented or Reserved
0
1
2
3
4
5
6
7
Figure
F
6
Table 8-23. P-Flash Protection Scenario Transitions
Figure 8-15. EEE Protection Register (EPROT)
8-15. To change the EEE protection that will be loaded during the reset
MC9S12XF - Family Reference Manual, Rev.1.19
X
X
0
RNV[6:4]
F
5
X
X
X
X
1
X
X
X
X
2
To Protection Scenario
F
4
Figure 8-14
X
X
X
X
X
X
X
X
3
Chapter 8 256 KByte Flash Module (S12XFTM256K2XFV1)
EPDIS
for a definition of the scenarios.
X
X
X
X
4
F
3
(1)
5
X
X
F
2
X
X
6
Table
EPS[2:0]
Table 8-23
X
7
F
1
8-3) as indicated
specifies
F
0
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