dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 98

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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15:10
12:8
Bit
9:0
Bit
7:0
15
14
13
14.6.12 PTP Temporary Rate Duration High Register (PTP_TRDH), Page 5
This register contains the high 10 bits of the duration in clock cycles to use the Temporary Rate as programmed in the PTP_RATEH
and PTP_RATEL registers. Since the Temporary Rate takes affect upon writing the PTP_RATEL register, this register should be
programmed before setting the Temporary Rate. This register does not need to be reprogrammed for each use of the Temporary
Rate registers.
14.7 PTP 1588 CONFIGURATION REGISTERS - PAGE 6
Page 6 PTP 1588 Configuration Registers are accessible by setting bits [2:0] = 110 of PAGESEL (13h).
14.7.1 PTP Clock Output Control Register (PTP_COC), Page 6
This register provides configuration for the PTP clock-synchronized output divide-by-N clock.
PTP_CLKOUT SEL
PTP_CLKOUT EN
PTP_TR_DURH
PTP_CLKOUT
PTP_CLKDIV
RESERVED
RESERVED
SPEEDSEL
Bit Name
Bit Name
TABLE 74. PTP Temporary Rate Duration High Register (PTP_TRDH), address 0x1F
TABLE 75. PTP Clock Output Control Register (PTP_COC), address 0x14
00 0000 0000, RW PTP Temporary Rate Duration High 10 bits:
0000 1010, RW
0000 00, RO
0 0000, RO
Default
Default
1, RW
0, RW
0, RW
Reserved: Writes ignored, Read as 0
This register sets the duration for the Temporary Rate in number of clock cycles.
The actual Time duration is dependent on the value of the Temporary Rate.
PTP Clock Output Enable:
1 = Enable PTP divide-by-N clock output.
0 = Disable PTP divide-by-N clock output.
PTP Clock Output Source Select:
1 = Select the Phase Generation Module (PGM) as the root clock for generating
the divide-by-N output.
0 = Select the Frequency-Controlled Oscillator (FCO) as the root clock for
generating the divide-by-N output.
For additional information related to the PTP clock output selection, refer to
application note AN–1729.
PTP Clock Output I/O Speed Select:
1 = Enable faster rise/fall time for the divide-by-N clock output pin.
0 = Enable normal rise/fall time for the divide-by-N clock output pin.
Reserved: Writes ignored, Read as 0
PTP Clock Divide-by Value:
This field sets the divide-by value for the output clock. The output clock is divided
from an internal 250 MHz clock. Valid values range from 2 to 255 (0x02 to 0xFF),
giving a nominal output frequency range of 125 MHz down to 980.4 kHz. Divide-
by values of 0 and 1 are not valid and will stop the output clock.
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Description
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