dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 21

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

Link Loss Timer as specified in the IEEE 802.3 specification.
In 100BASE-TX mode, an optional fast link loss detection may
be enabled by setting the SD_TIME control in the SD_CNFG
register. Enabling fast link loss detection will result in the
LED_LINK deassertion within approximately 1.3 µs of loss of
signal on the wire.
The LED_LINK pin in Mode 1 will be OFF when no LINK is
present.
The LED_LINK pin in Mode 2 and Mode 3 will be ON to indi-
cate Link is good and BLINK to indicate activity is present on
activity. The BLINK frequency is defined in BLINK_FREQ, bits
[7:6] of register LEDCR (18h).
Activity is defined as configured in LEDACT_RX, bit 8 of reg-
ister LEDCR (18h). If LEDACT_RX is 0, Activity is signaled
for either transmit or receive. If LEDACT_RX is 1, Activity is
only signaled for receive.
The LED_SPEED/FX_SD pin indicates 10 or 100 Mb/s data
rate of the port. The standard CMOS driver goes high when
operating in 100 Mb/s operation. The functionality of this LED
is independent of mode selected.
The LED_ACT pin in Mode 1 indicates the presence of either
transmit or receive activity. The LED will be ON for Activity
and OFF for No Activity. In Mode 2, this pin indicates the Col-
lision status of the port. The LED will be ON for Collision and
OFF for No Collision.
The LED_ACT pin in Mode 3 indicates Duplex status for 10
Mb/s or 100 Mb/s operation. The LED will be ON for Full Du-
plex and OFF for Half Duplex.
In 10 Mb/s half duplex mode, the collision LED is based on
the COL signal.
Since these LED pins are also used as strap options, the po-
larity of the LED is dependent on whether the pin is pulled up
or down.
9.6.1 LEDs
Since the Auto-Negotiation (AN) strap options share the LED
output pins, the external components required for strapping
and LED usage must be considered in order to avoid con-
tention.
Specifically, when the LED outputs are used to drive LEDs
directly, the active state of each output driver is dependent on
the logic level sampled by the corresponding AN input upon
power-up/reset. For example, if a given AN input is resistively
pulled low then the corresponding output will be configured
as an active high driver. Conversely, if a given AN input is
resistively pulled high, then the corresponding output will be
configured as an active low driver.
Refer to for an example of AN connections to external com-
ponents. In this example, the AN strapping results in Auto-
Negotiation disabled with 100 Full-Duplex forced.
The adaptive nature of the LED outputs helps to simplify po-
tential implementation issues of these dual purpose pins.
21
9.6.2 LED Direct Control
The DP83630 provides another option to directly control any
or all LED outputs through the LED Direct Control Register
(LEDCR), address 18h. The register does not provide read
access to LEDs.
9.7 HALF DUPLEX vs. FULL DUPLEX
The DP83630 supports both half and full duplex operation at
both 10 Mb/s and 100 Mb/s speeds.
Half-duplex relies on the CSMA/CD protocol to handle colli-
sions and network access. In Half-Duplex mode, Carrier
Sense (CRS) responds to both transmit and receive activity
in order to maintain compliance with the IEEE 802.3 specifi-
cation.
Since the DP83630 is designed to support simultaneous
transmit and receive activity it is capable of supporting full-
duplex switched applications with a throughput of up to 200
Mb/s when operating in either 100BASE-TX or 100BASE-FX.
Because the CSMA/CD protocol does not apply to full-duplex
operation, the DP83630 disables its own internal collision
sensing and reporting functions and modifies the behavior of
CRS such that it indicates only receive activity. This allows a
full-duplex capable MAC to operate properly.
All modes of operation (100BASE-TX, 100BASE-FX,
10BASE-T) can run either half-duplex or full-duplex. Addi-
tionally, other than CRS and collision reporting, all remaining
MII signaling remains the same regardless of the selected
duplex mode.
It is important to understand that while Auto-Negotiation with
the use of Fast Link Pulse code words can interpret and con-
figure to full-duplex operation, parallel detection can not rec-
ognize the difference between full and half-duplex from a fixed
10 Mb/s or 100 Mb/s link partner over twisted pair. As speci-
fied in the 802.3u specification, if a far-end link partner is
configured to a forced full-duplex 100BASE-TX ability, the
parallel detection state machine in the partner would be un-
able to detect the full-duplex capability of the far-end link
partner. This link segment would negotiate to a half-duplex
100BASE-TX configuration (same scenario for 10 Mb/s).
FIGURE 3. AN Strapping and LED Loading Example
www.national.com
30136202