dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 85

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

13:10
15:0
15:0
Bit
9:0
Bit
Bit
15
14
14.5.6 PTP Rate High Register (PTP_RATEH), Page 4
This register contains the upper bits of the PTP Rate control. In addition, it contains a direction control to indicate whether the
device is operating faster or slower than the reference clock frequency. When setting the PTP Rate, this register should be written
first, followed by a write to the PTP_RATEL register. The rate will take effect on the write to the PTP_RATEL register.
14.5.7 PTP Read Checksum (PTP_RDCKSUM), Page 4
This register keeps a running one’s complement checksum of 16-bit read data values for valid Page 4 read accesses. Clear the
checksum on a read to this register; read data from this register is not accumulated in the read checksum since the register is
cleared on read. However, read data from the write checksum register is accumulated to allow cross checking. Checksums are
not accumulated for PHY Control Frame register accesses, but are cleared on management or PHY Control Frame reads.
14.5.8 PTP Write Checksum (PTP_WRCKSUM), Page 4
This register keeps a running one’s complement checksum of 16-bit write data values for Page 4 write accesses. Clear the check-
sum on a read. Write data to this register or the read checksum register ARE accumulated in the write checksum to allow cross
checking. Read data from this register is accumulated in the read checksum to allow cross checking. Checksums are not accu-
mulated for PHY Control Frame register accesses, but are cleared on management or PHY Control Frame reads.
PTP_TMP_RATE
PTP_RATE_DIR
PTP_RATE_HI
WR_CKSUM
RD_CKSUM
RESERVED
Bit Name
Bit Name
Bit Name
TABLE 57. PTP Write Checksum (PTP_WRCKSUM), address 0x1B
TABLE 56. PTP Read Checksum (PTP_RDCKSUM), address 0x1A
XXXX XXXX XXXX
XXXX XXXX XXXX
00 0000 0000, RW PTP Rate High 10-bits:
TABLE 55. PTP Rate High Register (PTP_RATEH), address 0x19
XXXX, RO/ COR
XXXX, RO/ COR
00 00, RO
Default
Default
Default
0, RW
0, RW
PTP Rate Direction:
The setting of this bit controls whether the device will operate at a higher or lower
frequency than the reference clock.
0 : Higher Frequency. The PTP_RATE value will be added to the clock on every
cycle.
1 : Lower Frequency. The PTP_RATE value will be subtracted from the clock on
every cycle.
PTP Temporary Rate:
Setting this bit will cause the rate to be applied to the clock for the duration set in
the PTP Temporary Rate Duration Register (PTP_TRD).
1 : Temporary Rate
0 : Normal Rate
Reserved: Writes ignored, Read as 0
Writing to this register will set the high 10-bits of the Rate Control value. The Rate
Control value is in units of 2
PTP Page 4 Read Checksum.
PTP Page 4 Write Checksum.
85
-32
ns.
Description
Description
Description
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