dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 20

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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figuration pins, refer to the Reset summary in
Reset
Since the PHYAD[0] pin has weak internal pull-up resistor and
PHYAD[4:1] pins have weak internal pull-down resistors, the
default setting for the PHY address is 00001 (01h).
Refer to
external components. In this example, the PHYAD strapping
results in address 00011 (03h).
9.5.1 MII Isolate Mode
It is recommended that the user have a basic understanding
of Clause 22 of the 802.3u standard.
The DP83630 can be put into MII Isolate Mode by writing a 1
to bit 10 of the BMCR register. Strapping the PHY Address to
0 will force the device into Isolate Mode when powered up. It
should be noted that selecting Physical Address 0 via an
MDIO write to PHYCR will not put the device in the MII isolate
mode.
When in the MII Isolate Mode, the DP83630 does not respond
to packet data present at TXD[3:0] and TX_EN inputs and
9.6 LED INTERFACE
The DP83630 supports three configurable Light Emitting
Diode (LED) pins: LED_LINK, LED_SPEED/FX_SD, and
LED_ACT.
Several functions can be multiplexed onto the three LEDs us-
ing three different modes of operation. The LED operation
The LED_LINK pin in Mode 1 indicates the link status of the
port. In 100BASE-TX mode, link is established as a result of
input receive amplitude compliant with the TP-PMD specifi-
cations which will result in internal generation of signal detect.
Mode
Operation.
1
2
3
Figure
LED_CFG[1]
2for an example of a PHYAD connection to
don't care
0
1
LED_CFG[0]
1
0
0
FIGURE 2. PHYAD Strapping Example
Section 12.0
TABLE 3. LED Mode Selection
ON for Good Link
OFF for No Link
ON for Good Link
BLINK for Activity
ON for Good Link
BLINK for Activity
LED_LINK
20
presents a high impedance on the TX_CLK, RX_CLK,
RX_DV, RX_ER, RXD[3:0], COL, and CRS/CRS_DV outputs.
When in Isolate Mode, the DP83630 will continue to respond
to all serial management transactions over the MII.
While in Isolate Mode, the PMD output pair will not transmit
packet data but will continue to source 100BASE-TX scram-
bled idles or 10BASE-T normal link pulses.
The DP83630 can Auto-Negotiate or parallel detect to a spe-
cific technology depending on the receive signal at the PMD
input pair. A valid link can be established for the receiver even
when the DP83630 is in Isolate Mode.
9.5.2 Broadcast Mode
The DP83630 is also capable of accepting broadcast mes-
sages (register writes to PHY address 0x1F). Setting the
BC_WRITE to 1, bit 11 of the PHY Control Register 2 (PHY-
CR2) at address 0x1C, will configure the device to accept
broadcast messages independent of the local PHY Address
value.
mode can be selected by writing to the LED_CFG[1:0] register
bits in the PHY Control Register (PHYCR) at address 19h,
bits [6:5]. LED_CFG[1] is only controllable through register
access and cannot be set by a strap pin.
See
A 10 Mb/s Link is established as a result of the reception of
at least seven consecutive normal Link Pulses or the recep-
tion of a valid 10BASE-T packet. This will cause the assertion
of LED_LINK. LED_LINK will deassert in accordance with the
Table 3
ON in 100 Mb/s
OFF in 10 Mb/s
ON in 100 Mb/s
OFF in 10 Mb/s
ON in 100 Mb/s
OFF in 10 Mb/s
LED_SPEED
for LED Mode selection.
30136201
ON for Activity
OFF for No Activity
ON for Collision
OFF for No Collision
ON for Full Duplex
OFF for Half Duplex
LED_ACT