dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 19

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

The Auto-Negotiation Expansion Register (ANER) indicates
additional Auto-Negotiation status. The ANER provides sta-
tus on:
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9.2.3 Auto-Negotiation Parallel Detection
The DP83630 supports the Parallel Detection function as de-
fined in the IEEE 802.3u specification. Parallel Detection
requires both the 10 Mb/s and 100 Mb/s receivers to monitor
the receive signal and report link status to the Auto-Negotia-
tion function. Auto-Negotiation uses this information to con-
figure the correct technology in the event that the Link Partner
does not support Auto-Negotiation but is transmitting link sig-
nals that the 100BASE-TX or 10BASE-T PMAs recognize as
valid link signals.
If the DP83630 completes Auto-Negotiation as a result of
Parallel Detection, bits 5 and 7 within the ANLPAR register
will be set to reflect the mode of operation present in the Link
Partner. Note that bits 4:0 of the ANLPAR will also be set to
00001 based on a successful parallel detection to indicate a
valid 802.3 selector field. Software may determine that nego-
tiation completed via Parallel Detection by reading a zero in
the Link Partner Auto-Negotiation Able bit once the Auto-Ne-
gotiation Complete bit is set. If configured for parallel detect
mode and any condition other than a single good link occurs
then the parallel detect fault bit will be set.
9.2.4 Auto-Negotiation Restart
Once Auto-Negotiation has completed, it may be restarted at
any time by setting bit 9 (Restart Auto-Negotiation) of the BM-
CR to one. If the mode configured by a successful Auto-
Negotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the configura-
tion for the link. This function ensures that a valid configura-
tion is maintained if the cable becomes disconnected.
A renegotiation request from any entity, such as a manage-
ment agent, will cause the DP83630 to halt any transmit data
and link pulse activity until the break_link_timer expires
(~1500 ms). Consequently, the Link Partner will go into link
fail and normal Auto-Negotiation resumes. The DP83630 will
resume Auto-Negotiation after the break_link_timer has ex-
pired by issuing FLP (Fast Link Pulse) bursts.
9.2.5 Enabling Auto-Negotiation via Software
It is important to note that if the DP83630 has been initialized
upon power-up as a non-auto-negotiating device (forced
technology), and it is then required that Auto-Negotiation or
re-Auto-Negotiation be initiated via software, bit 12 (Auto-Ne-
gotiation Enable) of the Basic Mode Control Register (BMCR)
must first be cleared and then set for any Auto-Negotiation
function to take effect.
9.2.6 Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation take approximately
2-3 seconds to complete. In addition, Auto-Negotiation with
next page should take approximately 2-3 seconds to com-
plete, depending on the number of next pages sent.
Refer to Clause 28 of the IEEE 802.3u standard for a full de-
scription of the individual timers related to Auto-Negotiation.
Whether or not a Parallel Detect Fault has occurred
Whether or not the Link Partner supports the Next Page
function
Whether or not the DP83630 supports the Next Page
function
Whether or not the current page being exchanged by Auto-
Negotiation has been received
Whether or not the Link Partner supports Auto-Negotiation
19
9.3 AUTO-MDIX
When enabled, this function utilizes Auto-Negotiation to de-
termine the proper configuration for transmission and recep-
tion of data and subsequently selects the appropriate MDI pair
for MDI/MDIX operation. The function uses a random seed to
control switching of the crossover circuitry. This implementa-
tion complies with the corresponding IEEE 802.3 Auto-Nego-
tiation and Crossover Specifications.
Auto-MDIX is enabled by default and can be configured via
PHYCR (19h) register, bits [15:14].
Neither Auto-Negotiation nor Auto-MDIX is required to be en-
abled in forcing crossover of the MDI pairs. Forced crossover
can be achieved through the FORCE_MDIX bit, bit 14 of
PHYCR (19h) register.
9.4 AUTO-CROSSOVER IN FORCED MODE
When enabled, this function operates in a manner similar to
Auto-MDIX. If no link activity is seen, switching of the
crossover circuitry is based on a random seed. Valid link ac-
tivity can be link pulses (Auto-Negotiation link pulse or 10M
link pulses) or 100M signaling. Once valid link activity is seen,
crossover will stop to allow the receive and link functions will
proceed normally.
Auto-crossover in forced mode allows for shorter link times
because it does not require potentially lengthy Auto-Negotia-
tion transactions prior to link establishment. Link establish-
ment via Auto-crossover can be accomplished in full or half
duplex configuration, but both sides of the link must be forced
to the same duplex configuration.
Auto-crossover in forced mode is disabled by default and
must be configured via PCSR (16h) register, bit 15.
Forced crossover can be achieved while Auto-crossover is
enabled through the FORCE_MDIX bit, bit 14 of PHYCR
(19h) register.
NOTE: Auto-MDIX and Auto-crossover in forced mode are
mutually exclusive and should not be enabled concurrently.
Prior to enabling Auto-crossover in forced mode, Auto-Nego-
tiation and Auto-MDIX should be disabled.
9.5 PHY ADDRESS
The five PHY address strapping pins are shared with the RXD
[3:0] pins and COL pin as shown below.
The DP83630 can be set to respond to any of 32 possible
PHY addresses via strap pins. The information is latched into
the PHYCR register (address 19h, bits [4:0]) at device power-
up and hardware reset. Each DP83630 or port sharing an
MDIO bus in a system must have a unique physical address.
The DP83630 supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). Strapping PHY Address
0 puts the part into Isolate Mode. It should also be noted
that selecting PHY Address 0 via an MDIO write to PHYCR
will not put the device in Isolate Mode. See for more infor-
mation.
For further detail relating to the latch-in timing requirements
of the PHY Address pins, as well as the other hardware con-
Pin #
42
43
44
45
46
TABLE 2. PHY Address Mapping
PHYAD Function
PHYAD0
PHYAD1
PHYAD2
PHYAD3
PHYAD4
RXD Function
RXD_3
RXD_2
RXD_1
RXD_0
COL
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