dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 25

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

The pass/fail status of the BIST is stored in the BIST status
bit in the PHYCR register. The status bit defaults to 0 (BIST
fail) and will transition on a successful comparison. If an error
(mis-compare) occurs, the status bit is latched and is cleared
upon a subsequent write to the Start/Stop bit.
For transmit VOD testing, the Packet BIST Continuous Mode
can be used to allow continuous data transmission by setting
the BIST_CONT_MODE, bit 5, of CDCTRL1 (1Bh).
The number of BIST errors can be monitored through the
BIST Error Count in the CDCTRL1 (1Bh), bits [15:8].
10.0 MAC Interface
The DP83630 supports several modes of operation using the
MII interface pins. The options are defined in the following
sections and include:
— MII Mode
— RMII Mode
— Single Clock MII Mode (SCMII)
In addition, the DP83630 supports the standard 802.3u MII
Serial Management Interface.
The modes of operation can be selected by strap options or
register control. For RMII Slave mode, it is recommended to
use the strap option since it requires a 50 MHz clock instead
of the normal 25 MHz.
In each of these modes, the IEEE 802.3 serial management
interface is operational for device configuration and status.
The serial management interface of the MII allows for the
configuration and control of multiple PHY devices, gathering
of status, error information, and the determination of the type
and capabilities of the attached PHY(s).
10.1 MII INTERFACE
The DP83630 incorporates the Media Independent Interface
(MII) as specified in Clause 22 of the IEEE 802.3u standard.
This interface may be used to connect PHY devices to a MAC
in 10/100 Mb/s systems. This section describes the nibble
wide MII data interface.
The nibble wide MII data interface consists of a receive bus
and a transmit bus each with control signals to facilitate data
transfer between the PHY and the upper layer (MAC).
10.1.1 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the Media
Independent Interface. This interface includes a dedicated
receive bus and a dedicated transmit bus. These two data
buses, along with various control and status signals, allow for
the simultaneous exchange of data between the DP83630
and the upper layer agent (MAC).
The receive interface consists of a nibble wide data bus RXD
[3:0], a receive error signal RX_ER, a receive data valid flag
RX_DV, and a receive clock RX_CLK for synchronous trans-
fer of the data. The receive clock operates at either 2.5 MHz
to support 10 Mb/s operation modes or at 25 MHz to support
100 Mb/s operational modes.
The transmit interface consists of a nibble wide data bus TXD
[3:0], a transmit enable control signal TX_EN, and a transmit
clock TX_CLK which runs at either 2.5 MHz or 25 MHz.
Additionally, the MII includes the carrier sense signal CRS, as
well as a collision detect signal COL. The CRS signal asserts
to indicate the reception of data from the network or as a
function of transmit data in Half Duplex mode. The COL signal
asserts as an indication of a collision which can occur during
half-duplex operation when both a transmit and receive op-
eration occur simultaneously.
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10.1.2 Collision Detect
For Half Duplex, a 10BASE-T or 100BASE-TX collision is de-
tected when the receive and transmit channels are active
simultaneously. Collisions are reported by the COL signal on
the MII.
If the DP83630 is transmitting in 10 Mb/s mode when a colli-
sion is detected, the collision is not reported until seven bits
have been received while in the collision state. This prevents
a collision being reported incorrectly due to noise on the net-
work. The COL signal remains set for the duration of the
collision.
If a collision occurs during a receive operation, it is immedi-
ately reported by the COL signal.
When heartbeat is enabled (only applicable to 10 Mb/s oper-
ation), approximately 1µs after the transmission of each pack-
et, a Signal Quality Error (SQE) signal of approximately 10 bit
times is generated (internally) to indicate successful trans-
mission. SQE is reported as a pulse on the COL signal of the
MII.
Collision is not indicated during Full Duplex operation.
10.1.3 Carrier Sense
In 10 Mb/s operation, Carrier Sense (CRS) is asserted due to
receive activity once valid data is detected via the Smart
Squelch function. During 100 Mb/s operation CRS is asserted
when a valid link (SD) and two non-contiguous zeros are de-
tected on the line.
For 10 or 100 Mb/s Half Duplex operation, CRS is asserted
during either packet transmission or reception.
For 10 or 100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.
CRS is deasserted following an end of packet.
10.2 REDUCED MII INTERFACE
The DP83630 incorporates the Reduced Media Independent
Interface (RMII) as specified in the RMII specification (rev 1.2)
from the RMII Consortium. This interface may be used to
connect PHY devices to a MAC in 10/100 Mb/s systems using
a reduced number of pins. In this mode, data is transferred 2-
bits at a time using the 50 MHz RMII_REF clock for both
transmit and receive. The following pins are used in RMII
mode:
— TX_EN
— TXD[1:0]
— RX_ER (optional for MAC)
— CRS/CRS_DV
— RXD[1:0]
— X1 (25 MHz in RMII Master mode, 50 MHz in RMII Slave
mode)
— RX_CLK, TX_CLK, CLK_OUT (50 MHz RMII reference
clock in RMII Master mode only)
In addition, the RMII mode supplies an RX_DV signal which
allows for a simpler method of recovering receive data without
having to separate RX_DV from the CRS_DV indication. This
is especially useful for systems which do not require CRS,
such as systems that only support full-duplex operation. This
signal is also useful for diagnostic testing where it may be
desirable to loop external Receive RMII data directly to the
transmitter.
The RX_ER output may be used by the MAC to detect error
conditions. It is asserted for symbol errors received during a
packet, False Carrier events, and also for FIFO underrun or
overrun conditions. Since the PHY is required to corrupt re-
ceive data on an error, a MAC is not required to use RX_ER.
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