dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 5

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

15.0 Absolute Maximum Ratings ......................................................................................................... 102
16.0 Recommended Operating Conditions ........................................................................................... 102
17.0 Thermal Characteristic ............................................................................................................... 102
18.0 AC and DC Specifications ........................................................................................................... 102
19.0 Physical Dimensions .................................................................................................................. 124
20.0 Ordering Information .................................................................................................................. 124
14.7 PTP 1588 CONFIGURATION REGISTERS - PAGE 6 ............................................................... 98
18.1 DC SPECIFICATIONS ........................................................................................................ 102
18.2 AC SPECIFICATIONS ........................................................................................................ 104
14.6.8 PTP Receive Configuration Register 2 (PTP_RXCFG2), Page 5 ....................................... 95
14.6.9 PTP Receive Configuration Register 3 (PTP_RXCFG3), Page 5 ....................................... 96
14.6.10 PTP Receive Configuration Register 4 (PTP_RXCFG4), Page 5 ..................................... 97
14.6.11 PTP Temporary Rate Duration Low Register (PTP_TRDL), Page 5 ................................. 97
14.6.12 PTP Temporary Rate Duration High Register (PTP_TRDH), Page 5 ................................ 98
14.7.1 PTP Clock Output Control Register (PTP_COC), Page 6 ................................................. 98
14.7.2 PHY Status Frame Configuration Register 1 (PSF_CFG1), Page 6 .................................... 99
14.7.3 PHY Status Frame Configuration Register 2 (PSF_CFG2), Page 6 .................................... 99
14.7.4 PHY Status Frame Configuration Register 3 (PSF_CFG3), Page 6 .................................... 99
14.7.5 PHY Status Frame Configuration Register 4 (PSF_CFG4), Page 6 .................................... 99
14.7.6 PTP SFD Configuration Register (PTP_SFDCFG), Page 6 ............................................. 100
14.7.7 PTP Interrupt Control Register (PTP_INTCTL), Page 6 .................................................. 100
14.7.8 PTP Clock Source Register (PTP_CLKSRC), Page 6 .................................................... 100
14.7.9 PTP Ethernet Type Register (PTP_ETR), Page 6 .......................................................... 100
14.7.10 PTP Offset Register (PTP_OFF), Page 6 ................................................................... 101
14.7.11 PTP GPIO Monitor Register (PTP_GPIOMON), Page 6 ............................................... 101
14.7.12 PTP Receive Hash Register (PTP_RXHASH), Page 6 ................................................. 101
18.2.1 Power Up Timing ...................................................................................................... 104
18.2.2 Reset Timing ........................................................................................................... 105
18.2.3 MII Serial Management Timing ................................................................................... 106
18.2.4 100 Mb/s MII Transmit Timing .................................................................................... 106
18.2.5 100 Mb/s MII Receive Timing ..................................................................................... 107
18.2.6 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing .............................. 107
18.2.7 100BASE-TX and 100BASE-FX MII Transmit Packet Deassertion Timing ........................ 108
18.2.8 100BASE-TX Transmit Timing (t
18.2.9 100BASE-TX and 100BASE-FX MII Receive Packet Latency Timing ............................... 109
18.2.10 100BASE-TX and 100BASE-FX MII Receive Packet Deassertion Timing ....................... 109
18.2.11 10 Mb/s MII Transmit Timing .................................................................................... 110
18.2.12 10 Mb/s MII Receive Timing ..................................................................................... 110
18.2.13 10BASE-T MII Transmit Timing (Start of Packet) ......................................................... 111
18.2.14 10BASE-T MII Transmit Timing (End of Packet) .......................................................... 111
18.2.15 10BASE-T MII Receive Timing (Start of Packet) .......................................................... 112
18.2.16 10BASE-T MII Receive Timing (End of Packet) ........................................................... 112
18.2.17 10 Mb/s Heartbeat Timing ....................................................................................... 113
18.2.18 10 Mb/s Jabber Timing ........................................................................................... 113
18.2.19 10BASE-T Normal Link Pulse Timing ......................................................................... 114
18.2.20 Auto-Negotiation Fast Link Pulse (FLP) Timing ........................................................... 114
18.2.21 100BASE-TX Signal Detect Timing ........................................................................... 115
18.2.22 100 Mb/s Internal Loopback Timing .......................................................................... 115
18.2.23 10 Mb/s Internal Loopback Timing ............................................................................ 116
18.2.24 RMII Transmit Timing (Slave Mode) .......................................................................... 116
18.2.25 RMII Transmit Timing (Master Mode) ......................................................................... 117
18.2.26 RMII Receive Timing (Slave Mode) ........................................................................... 118
18.2.27 RMII Receive Timing (Master Mode) .......................................................................... 119
18.2.28 RX_CLK Timing (RMII Master Mode) ......................................................................... 120
18.2.29 CLK_OUT Timing (RMII Slave Mode) ........................................................................ 120
18.2.30 Single Clock MII (SCMII) Transmit Timing ................................................................. 121
18.2.31 Single Clock MII (SCMII) Receive Timing ................................................................... 122
18.2.32 100 Mb/s X1 to TX_CLK Timing ................................................................................ 123
R/F
& Jitter) .................................................................. 108
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