dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 26

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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Since the reference clock operates at 10 times the data rate
for 10 Mb/s operation, transmit data is sampled every 10
clocks. Likewise, receive data will be generated every 10th
clock so that an attached device can sample the data every
10 clocks.
RMII Slave mode requires a 50 MHz oscillator to be connect-
ed to the device X1 pin. A 50 MHz crystal is not supported.
RMII Master mode can use either a 25 MHz oscillator con-
nected to X1 or a 25 MHz crystal connected to X1 and X2.
To tolerate potential frequency differences between the 50
MHz reference clock and the recovered receive clock, the re-
ceive RMII function includes a programmable elasticity buffer.
The elasticity buffer is programmable to minimize propagation
delay based on expected packet size and clock accuracy.
10.2.1 RMII Master Mode
In RMII Master Mode, the DP83630 uses a 25 MHz crystal on
X1/X2 and internally generates the 50 MHz RMII reference
clock for use by the RMII logic. The 50 MHz clock is output
on RX_CLK, TX_CLK, and CLK_OUT for use as the refer-
ence clock for an attached MAC. RX_CLK operates at 25 MHz
during reset.
10.2.2 RMII Slave Mode
In RMII Slave Mode, the DP83630 takes a 50 MHz reference
clock input on X1 from an external oscillator or another
DP83630 in RMII Master Mode. The 50 MHz is internally di-
vided down to 25 MHz for use as the reference clock for non-
RMII logic. RX_CLK, TX_CLK, and CLK_OUT should not be
used as the RMII reference clock in this mode but may be
used for other system devices.
10.3 SINGLE CLOCK MII MODE
Single Clock MII (SCMII) Mode allows MII operation using a
single 25 MHz reference clock. Normal MII Mode requires
10.4 IEEE 802.3u MII SERIAL MANAGEMENT INTERFACE
10.4.1 Serial Management Register Access
The serial management MII specification defines a set of thir-
ty-two 16-bit status and control registers that are accessible
through the management interface pins MDC and MDIO. The
DP83630 implements all the required MII registers as well as
several optional registers. These registers are fully described
in
management access protocol follows.
Section 14.0 Register
Start Threshold RBR[1:0]
Start Threshold RBR[1:0]
01 (default)
01 (default)
10
11
00
10
11
00
TABLE 6. Supported SCMII Packet Sizes at +/-50 ppm Frequency Accuracy
Block. A description of the serial
TABLE 5. Supported Packet Sizes at +/-50 ppm Frequency Accuracy
100 Mb
100 Mb
4 bits
4 bits
8 bits
8 bits
10 bits
14 bits
2 bits
6 bits
Latency Tolerance
Latency Tolerance
10 Mb
8 bits
8 bits
8 bits
8 bits
12 bits
10 Mb
8 bits
4 bits
8 bits
26
This allows for supporting a range of packet sizes including
jumbo frames.
The elasticity buffer will force Frame Check Sequence errors
for packets which overrun or underrun the FIFO. Underrun
and overrun conditions can be reported in the RMII and By-
pass Register (RBR).
elasticity buffer FIFO (in 4-bit increments) based on expected
maximum packet size and clock accuracy. It assumes both
clocks (RMII Reference clock and far-end Transmitter clock)
have the same accuracy.
Packet lengths can be scaled linearly based on accuracy (+/-
25 ppm would allow packets twice as large). If the threshold
setting must support both 10 Mb and 100 Mb operation, the
setting should be made to support both speeds.
three clocks, a reference clock for physical layer functions, a
transmit MII clock, and a receive MII clock. Similar to RMII
mode, Single Clock MII mode requires only the reference
clock. In addition to reducing the number of pins required, this
mode allows the attached MAC device to use only the refer-
ence clock domain. AC Timing requirements for SCMII oper-
ation are similar to the RMII timing requirements.
For 10 Mb operation, as in RMII mode, data is sampled and
driven every 10 clocks since the reference clock is at 10 times
the data rate.
Separate control bits allow enabling the Transmit and Re-
ceive Single Clock modes separately, allowing just transmit
or receive to operate in this mode. Control of Single Clock MII
mode is through the RBR register.
Single Clock MII mode incorporates the use of the RMII elas-
ticity buffer, which is required to tolerate potential frequency
differences between the 25 MHz reference clock and the re-
covered receive clock. Settings for the elasticity buffer for
SCMII mode are detailed in
10.4.2 Serial Management Access Protocol
The serial control interface consists of two pins, Management
Data Clock (MDC) and Management Data Input/Output
(MDIO). MDC has a maximum clock rate of 25 MHz and no
minimum rate. The MDIO line is bi-directional and may be
shared by up to 32 devices. The MDIO frame format is shown
below in
The MDIO pin requires a pull-up resistor (1.5 kΩ) which, dur-
ing IDLE and turnaround, will pull MDIO high. The DP83630
also includes an option to enable an internal pull-up on the
MDIO pin, MDIO_PULL_EN bit in the CDCTRL1 register. In
Recommended Packet Size at +/- 50 ppm
Table
4,000 bytes
4,000 bytes
9,600 bytes
9,600 bytes
Recommended Packet Size at +/- 50 ppm
100 Mb
12,000 bytes
16,800 bytes
2,400 bytes
7,200 bytes
7.
100 Mb
Table 5
Table
indicates how to program the
6.
9,600 bytes
9,600 bytes
9,600 bytes
9,600 bytes
14,400 bytes
9,600 bytes
4,800 bytes
9,600 bytes
10 Mb
10 Mb