dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 118

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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T2.26.1
T2.26.2
T2.26.3
T2.26.4
T2.26.5
Parameter
18.2.26 RMII Receive Timing (Slave Mode)
Note: Per the RMII Specification, output delays assume a 25 pF load.
Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. CRS_DV may toggle synchronously at the end of
Note: CRS ON delay is measured from the first bit of the JK symbol on the PMD Input Pair to initial assertion of CRS_DV.
Note: CRS OFF delay is measured from the first bit of the TR symbol on the PMD Input Pair to initial de-assertion of CRS_DV.
Note: Receive Latency is measured from the first bit of the symbol pair on the PMD Input Pair. Typical values are with the Elasticity Buffer set to the default value
Note: Enabling IEEE 1588 Receive Timestamp insertion will increase the Receive Data Latency by 40 bit times.
Note: Enabling PHY Status Frames will introduce variability in Receive Data Latency due to insertion of PHY Status Frames into the receive datapath.
the packet to indicate CRS de-assertion.
(01).
X1 Clock Period
RXD[1:0], CRS_DV, and RX_ER
output delay from X1 rising edge
CRS ON delay
CRS OFF delay
RXD[1:0] and RX_ER latency
Description
50 MHz Reference Clock
100BASE-TX mode
100BASE-FX mode
100BASE-TX mode
100BASE-FX mode
100BASE-TX mode
100BASE-FX mode
Notes
118
Min
2
18.5
Typ
20
27
17
38
27
9
Max
14
30136255
Units
bits
bits
bits
ns
ns