dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 15

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

PHYAD0
PHYAD1
PHYAD2
PHYAD3
PHYAD4
AN_EN
AN1
AN0
8.8 STRAP OPTIONS
The DP83630 uses many of the functional pins as strap op-
tions to place the device into specific modes of operation. The
values of these pins are sampled at power up or hard reset.
During software resets, the strap options are internally reload-
ed from the values sampled at power up or hard reset. The
strap option pin assignments are defined below. The func-
tional pin name is indicated in parentheses.
Signal Name
COL
RXD_3
RXD_2
RXD_1
RXD_0
LED_LINK
LED_SPEED/
FX_SD
LED_ACT
Pin Name
S, O, PU
S, O, PD
S, O, PD
S, O, PD
S, O, PD
S, O, PU
S, O, PU
S, O, PU
Type
Pin #
42
43
44
45
46
28
27
26
PHY ADDRESS [4:0]: The DP83630 provides five PHY address pins,
the state of which are latched into the PHYCTRL register at system
Hardware-Reset.
The DP83630 supports PHY Address strapping values 0 (<00000>)
through 31 (<11111>).A PHY Address of 0 puts the part into the MII
Isolate Mode. The MII isolate mode must be selected by strapping
PHY Address 0; changing to Address 0 by register write will not put the
PHY in the MII isolate mode.
PHYAD[0] pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-down resistors.
AUTO-NEGOTIATION ENABLE: When high, this enables Auto-
Negotiation with the capability set by AN0 and AN1 pins. When low,
this puts the part into Forced Mode with the capability set by AN0 and
AN1 pins.
AN0 / AN1: These input pins control the forced or advertised operating
mode of the DP83630 according to the following table. The value on
these pins is set by connecting the input pins to GND (0) or V
through 2.2 kΩ resistors. These pins should NEVER be connected
directly to GND or V
The value set at this input is latched into the DP83630 at Hardware-
Reset.
The float/pull-down status of these pins are latched into the Basic Mode
Control Register and the Auto_Negotiation Advertisement Register
during Hardware-Reset.
The default is 111 since these pins have internal pull-ups.
FIBER MODE DUPLEX SELECTION: If Fiber mode is strapped using
the FX_EN_Z pin (FX_EN_Z = 0), the AN0 strap value is used to select
half or full duplex. AN_EN and AN1 are ignored in Fiber mode since it
is 100 Mb only and does not support Auto-Negotiation. In Fiber mode,
AN1 should not be connected to any system components except the
fiber transceiver.
FX_EN_
FX_EN_
15
Z
1
1
1
1
0
0
Z
1
1
1
1
A 2.2 kΩ resistor should be used for pull-down or pull-up to
change the default strap option. If the default option is re-
quired, then there is no need for external pull-up or pull down
resistors. Since these pins may have alternate functions after
reset is deasserted, they should not be connected directly to
V
CC
or GND.
AN_EN
AN_EN
X
X
0
0
0
0
1
1
1
1
CC
AN1
AN1
X
X
0
0
1
1
0
0
1
1
.
Description
AN0
AN0
0
1
0
1
0
1
0
1
0
1
10BASE-T, Half-Duplex
10BASE-T, Full-Duplex
100BASE-TX, Half-Duplex
100BASE-TX, Full-Duplex
100BASE-FX, Half-Duplex
100BASE-FX, Full-Duplex
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
100BASE-TX, Full-Duplex
10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
Advertised Mode
Forced Mode
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