dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 35

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

The COL signal remains set for the duration of the collision.
If the ENDEC is receiving when a collision is detected it is
reported immediately (through the COL pin).
When heartbeat is enabled, approximately 1 µs after the
transmission of each packet, a Signal Quality Error (SQE)
signal of approximately 10-bit times is generated to indicate
successful transmission. SQE is reported as a pulse on the
COL signal of the MII.
The SQE test is inhibited when the PHY is set in full duplex
mode. SQE can also be inhibited by setting the
HEARTBEAT_DIS bit (1) in the 10BTSCR register (0x1A).
11.4.4 Carrier Sense
Carrier Sense (CRS) may be asserted due to receive activity
once valid data is detected via the squelch function.
For 10 Mb/s Half Duplex operation, CRS is asserted during
either packet transmission or reception.
For 10 Mb/s Full Duplex operation, CRS is asserted only dur-
ing receive activity.
CRS is deasserted following an end of packet.
11.4.5 Normal Link Pulse Detection/Generation
The link pulse generator produces pulses as defined in the
IEEE 802.3 10BASE-T standard. Each link pulse is nominally
100 ns in duration and transmitted every 16 ms in the absence
of transmit data.
Link pulses are used to check the integrity of the connection
with the remote end. If valid link pulses are not received, the
link detector disables the 10BASE-T twisted pair transmitter,
receiver and collision detection functions.
When the link integrity function is disabled (FORCE_LINK_10
of the 10BTSCR register), a good link is forced and the
10BASE-T transceiver will operate regardless of the pres-
ence of link pulses.
11.4.6 Jabber Function
The jabber function monitors the DP83630's output and dis-
ables the transmitter if it attempts to transmit a packet of
longer than legal size. A jabber timer monitors the transmitter
and disables the transmission if the transmitter is active for
approximately 85 ms.
Once disabled by the Jabber function, the transmitter stays
disabled for the entire time that the ENDEC module's internal
transmit enable is asserted. This signal has to be de-asserted
for approximately 500 ms (the “unjab” time) before the Jabber
function re-enables the transmit outputs.
The Jabber function is only relevant in 10BASE-T mode.
11.4.7 Automatic Link Polarity Detection and Correction
The DP83630's 10BASE-T transceiver module incorporates
an automatic link polarity detection circuit. When three con-
secutive inverted link pulses are received, bad polarity is
reported. The bad polarity condition is latched in the
10BTSCR register.
The DP83630's 10BASE-T transceiver module corrects for
this error internally and will continue to decode received data
correctly. This eliminates the need to correct the wiring error
immediately.
A polarity reversal can be caused by a wiring error at either
end of the cable, usually at the Main Distribution Frame (MDF)
or patch panel in the wiring closet.
35
11.4.8 Transmit and Receive Filtering
External 10BASE-T filters are not required when using the
DP83630, as the required signal conditioning is integrated in-
to the device.
Only isolation transformers and impedance matching resis-
tors are required for the 10BASE-T transmit and receive
interface. The internal transmit filtering ensures that all the
harmonics in the transmit signal are attenuated by at least
30 dB.
11.4.9 Transmitter
The encoder begins operation when the Transmit Enable in-
put (TX_EN) goes high and converts NRZ data to pre-em-
phasized Manchester data for the transceiver. For the
duration of TX_EN, the serialized Transmit Data (TXD) is en-
coded for the transmit-driver pair (PMD Output Pair). TXD
must be valid on the rising edge of Transmit Clock (TX_CLK).
Transmission ends when TX_EN de-asserts. The last transi-
tion is always positive; it occurs at the center of the bit cell if
the last bit is a one, or at the end of the bit cell if the last bit is
a zero.
11.4.10 Receiver
The decoder consists of a differential receiver and a PLL to
separate a Manchester encoded data stream into internal
clock signals and data. The differential input must be exter-
nally terminated with a differential 100 Ω termination network
to accommodate UTP cable.
The decoder detects the end of a frame when no additional
mid-bit transitions are detected. Within one and a half bit times
after the last bit, carrier sense is de-asserted. Receive clock
stays active for five more bit times after CRS goes low, to
guarantee the receive timings of the controller.
12.0 Reset Operation
The DP83630 includes an internal power-on reset (POR)
function and does not need to be explicitly reset for normal
operation after power up. If required during normal operation,
the device can be reset by a hardware or software reset.
12.1 HARDWARE RESET
A hardware reset is accomplished by applying a low pulse
(TTL level), with a duration of at least 1 µs, to the RESET_N
pin. This will reset the device such that all registers will be
reinitialized to default values and the hardware configuration
values will be re-latched into the device (similar to the power-
up/reset operation).
12.2 FULL SOFTWARE RESET
A full-chip software reset is accomplished by setting the RE-
SET bit (bit 15) of the Basic Mode Control Register (BMCR).
The period from the point in time when the reset bit is set to
the point in time when software reset has concluded is ap-
proximately 1 µs.
The software reset will reset the device such that all registers
will be reset to default values and the hardware configuration
values will be maintained. Software driver code must wait 3
µs following a software reset before allowing further serial MII
operations with the DP83630.
12.3 SOFT RESET
A partial software reset can be initiated by setting the
SOFT_RESET bit (bit 9) in the PHYCR2 Register. Setting this
bit will reset all transmit and receive operations, but will not
reset the register space. All register configurations will be
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