gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 72

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

Functional Description
Figure 6-38 Power Management Circuit
6.2.11.1 IDLE Mode
The user can put the processor into idle mode by writing 1 to the bit PCON.0. The instruction that sets the
idle bit is the last instruction that will be executed before the device goes into IDLE mode, the clock to the
CPU is halted, but not to the interrupt and peripherals such as Timer, Watchdog timer and serial port
blocks. This forces the CPU state to be frozen; the Program counter, the Stack Pointer, the Program
Status Word, the Accumulator and the other registers hold their contents. The ALE and /PSEN pins are
held high during the IDLE state. The port pins hold the logical states they had at the time the IDLE state
had started. The IDLE mode can be terminated in two ways. Since the interrupt controller is still active,
the activation of any enabled interrupt can wake up the processor. This will automatically clear the IDL bit,
terminate the IDLE mode, and the Interrupt Service Routine (ISR) will be executed. After the ISR,
execution of the program will continue from the instruction that put the processor into IDLE mode.
The IDLE mode can also be exited by activating the reset. The processor can be put into the reset by
applying a high on the external RST pin, a Power-On-Rest condition or a Watchdog timer reset. The
external reset pin has to be held high for at least six machine cycles i.e. 24 clock periods to be recognized
as a valid reset. At the reset condition the program counter is reset to 0000h and all the SFRs are set to
the reset condition. Since the clock has been already running, without delay execution starts immediately.
In the IDLE mode, the Watchdog timer continues to run, and if enabled, a time-out will cause a watchdog
timer interrupt that will wake up the processor. The software must reset the Watchdog timer in order to
preempt the reset that will occur after 512 clock periods of the time-out. When the MiDAS1.0 family is
exiting from an IDLE mode with a reset, the instruction will start from address 0000h. So there is no
danger of unexpected writings.
6.2.11.2 Power Down Mode
The processor can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does
this will be the last instruction to be executed before the processor goes into Power Down mode. In the
Power Down mode, all the clocks are stopped and the processor comes to a halt. All activity is completely
stopped and the power consumption is reduced to the lowest possible value. In this state, ALE and
/PSEN pins are pulled low. The port pins output the values held by their respective SFRs.
The MiDAS1.0 family will exit the Power Down mode with a reset or by the two external interrupts, /INT0
and /INT1, enabled as level sensitive configuration (0 or 1). An external reset can be used to exit the
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