gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 36
gc80c520a
Manufacturer Part Number
gc80c520a
Description
Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC80C520A.pdf
(187 pages)
- Current page: 36 of 187
- Download datasheet (2Mb)
The power-On/Fail reset and interrupt signals are generated when V
reference voltages as shown in Figure 6-12.
Figure 6-12 Power-On Reset/Power-fail Reset and Power-fail interrupt (V
The LVD block is described in Figure 6-13. It always remains activated except when BGS = 0 and a
MiDAS1.0 processor is in power-down mode.
If your system needs to detect the power–fail in power-down mode(PCON[1]=1), you should set the BGS
bit (EXIF[0]) to logic 1. Then, the band–gap reference and the power-fail detection circuits will remain
activated in power-down mode. As a result, the power consumption of power-down mode increases. If the
LVD block is deactivated, less than 1 μA of current will flow through the MiDAS1.0 processor. The current
will increase to about 180 μA by activation of the LVD block.
WDCON[6] (POR) : After Power-on reset, POR will be set.
WDCON[5] (EPFI) : Power-fail interrupt enable.
WDCON[4] (PFI) : Power-fail interrupt flag. When VCC drops below V
PFI will be set. If Vdd < VPFI, PFI is always set to “1”.
PCON[4] (POF): After Power-on reset, POF will be set.
POR Pulse
PFI Pulse
5.0
4.0
2.5
0
A
2.5V
B
SLOPE_R
4.0V
Page 36 of 187
4.0V
Functional Description
C
CC
SLOPE_F
2.5V
D
rises above or falls below the
PFI
PFI
TIME
=4.0V and V
or goes to above V
RST
=2.5V)
PFI
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