gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 23
gc80c520a
Manufacturer Part Number
gc80c520a
Description
Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC80C520A.pdf
(187 pages)
- Current page: 23 of 187
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6.1.3.1.4 Index Addressing Mode
6.1.3.1.5 Register Addressing Mode
6.1.3.1.6 Register-Specific Addressing Mode
6.1.4 CPU Timing
The CPU timing for the MiDAS1.0 family is an important aspect, especially for those who wish to use
software instructions to generate timing delays. Also, it provides the user with an insight into the timing
differences between the MiDAS1.0 family and the standard 80C52 as shown in Figure 6-2. In the
MiDAS1.0 family, each machine cycle is four clock periods long. Each clock period is designated a state.
Thus each machine cycle is made up of four states, S1, S2, S3 and S4 in that order. Due to the reduced
Only program memory can be accessed with indexed addressing, and it can only be read. This
addressing mode is intended for reading look-up tables in program memory. A 16-bit base register
(either DPTR or the PC) points to the base of the table, and the accumulator is set up with the table
entry number. The address of the table entry in program memory is formed by adding the
accumulator data to the base pointer data. Another type of indexed addressing is used in the “case
jump” instruction. In this case, the destination address of a jump instruction is calculated as the sum
of the base pointer data and the accumulator data.
Examples:
MOVC A, @A + DPTR
MOVC A, @A + PC
JMP @A + DPTR
The register banks, containing registers R0 through R7, can be accessed by certain instructions
which carry a 3-bit register specification within the opcode of the instruction. Instructions that access
the registers this way are code efficient, since this mode eliminates an address byte. When the
instruction is executed, one of the eight registers in the selected bank is accessed. One of four banks
is selected at execution time by the two bank select bits (RS0 and RS1) in the PSW.
Some instructions are specific to a certain register. For example, some instructions always operate
on the accumulator, or data pointer, etc., so no address byte is needed to point to it.
MiDAS1.0 Family
Jump to sum of accumulator and DPTR
The address is the sum of DPTR and accumulator.
The address is the sum of PC and accumulator
Page 23 of 187
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