gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 172
gc80c520a
Manufacturer Part Number
gc80c520a
Description
Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC80C520A.pdf
(187 pages)
- Current page: 172 of 187
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15.24 Slave Address Mask Enable Register (SADEN)
Bit No.
B9h
PT1H
PX1H
PT0H
PX0H
PT1
PX1
PT0
PX0
R/W(0)
SADEN.7
7
Timer 1 Interrupt Priority. These bits control the priority of the Timer 1 interrupt up to
four levels.
External Interrupt 1 Priority. These bits control the priority of the external interrupt 1 up
to four levels.
Timer 0 Interrupt Priority. These bits control the priority of the Timer 0 interrupt up to
four levels.
External Interrupt 0 Priority. These bits control the priority of the external interrupt 0 up
to four levels.
PT1H
PT0H
PX1H
PX0H
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R/W(0)
SADEN.6
6
R/W(0)
SADEN.5
PT1
PX1
PT0
PX0
5
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R/W(0)
SADEN.4
Page 172 of 187
Description
Priority level 0
Priority level 1
Priority level 2
Priority level 3
Description
Priority level 0
Priority level 1
Priority level 2
Priority level 3
Description
Priority level 0
Priority level 1
Priority level 2
Priority level 3
Description
Priority level 0
Priority level 1
Priority level 2
Priority level 3
4
SADEN.3
R/W(0)
3
R/W(0)
SADEN.2
2
Appendix B: SFR description
R/W(0)
SADEN.1
1
SADEN.0
R/W(0)
0
SADEN
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