gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 164

• Manufacturer Part Number: gc80c520a
• Description: Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

15.12 Clock Control Register (CKCON)
Bit No.
WD1, WD0
8Eh
Symbol
T2M
T1M
T0M
-
R/W(0)
WD1
7
Function
Watchdog Timer Mode Select. These bits determine the Watchdog timer time-out
period. The timer divides the crystal frequency by a programmable value as shown
below. The divider value is expressed in clock (crystal) cycles. Note that the reset time-
out is 512 clocks longer than the interrupt, regardless of whether the interrupt is
enabled.
Timer 2 Clock Select. This bit controls the division of the system clock that drives Timer
2. This bit has no effect when the timer is in baud rate generator or clock output modes.
Clearing this bit to 0 maintains 80C52 compatibility. This bit has no effect on instruction
cycle timing.
0: Timer 2 uses a divide by 12 of the crystal frequency.
1: Timer 2 uses a divide by 4 of the crystal frequency.
Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer
1. Clearing this bit to 0 maintains 80C52 compatibility. This bit has no effect on
instruction cycle timing.
0: Timer 1 uses a divide by 12 of the crystal frequency.
1: Timer 1 uses a divide by 4 of the crystal frequency.
Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer
0. Clearing this bit to 0 maintains 80C52 compatibility. This bit has no effect on
instruction cycle timing.
0: Timer 0 uses a divide by 12 of the crystal frequency.
1: Timer 0 uses a divide by 4 of the crystal frequency.
Reserved. These bits will read 0
WD1
0
0
1
1
R/W(0)
WD0
6
WD0
R/W(0)
0
1
0
1
T2M
5
Interrupt Divider
2
2
2
2
17
20
23
26
R/W(0)
Page 164 of 187
T1M
4
R/W(0)
T0M
3
2
-
-
Appendix B: SFR description
Reset Divider
2
2
2
2
17
20
23
26
+ 512
+ 512
+ 512
+ 512
1
-
-
0
-
-
CKCON