gc80c520a CORERIVER Semiconductor, gc80c520a Datasheet - Page 22
gc80c520a
Manufacturer Part Number
gc80c520a
Description
Midas1.0 Family Mask Rom/eprom/romless 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
1.GC80C520A.pdf
(187 pages)
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6.1.3.1.2 Direct Addressing Mode
6.1.3.1.3 Indirect Addressing Mode
Examples:
MOV R3, #0FFh
ORL PSW, #00000101b
MOV DPTR, #1243h
In direct addressing mode, the operand is specified by an 8-bit address field, which is part of the
instruction.
Note: The lower 128 bytes of the internal RAM can be addressed in this mode. It is the only method
of accessing the SFRs.
Examples:
MOV A, TCON
MOV R4, variable
In indirect addressing mode, the operand is specified by an 8-bit or 16-bit address that is stored in a
register. For 8-bit addresses, the content of either R0 or R1 (in the selected register bank) is used.
For 16-bit addresses, 16-bit wide data pointer (DPTR) can be used.
Note: The lower and upper part of the internal RAM can be addressed by using 8-bit addresses. The
external data memory can be addressed by 16-bit addresses.
Examples:
MOV A, @R0
MOVX A, @DPTR
R3 is loaded with constant value 0FFh
TCON is the 8-bit address of the SFR TCON.
The variable is the 8-bit address of a memory location in the
lower part of the RAM.
External data memory is addressed by contents of the selected
data pointer DPTR (16-bit address)
Logical OR operation with PSW and 0000 0101b
Load data pointer with constant value 1234h
RAM is addressed by contents of R0 (8-bit address)
Page 22 of 187
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