gc80c521a CORERIVER Semiconductor, gc80c521a Datasheet
gc80c521a
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... Brief Manual of MiDAS1.0B Family 8-bit Turbo Microcontrollers CORERIVER Semiconductor reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time. CORERIVER shall give customers at least a three month advance notice of intended discontinuation of a product or a service through its homepage ...
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Contents 1. Product Overview 2. Features 3. Block Diagram 4. Pin Configurations 5. Pin Descriptions 6. Function Descriptions CPU Descriptions - Memory Organization - SFR Map and Description - Instruction Set Summary - CPU Timing Peripheral Descriptions - I/O Ports ...
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Product Overview CORERIVER’s MiDAS1.0B Family is a group of fast 80C52 compatible microcontrollers. The instruction execution of MiDAS1.0B Family is max. that of traditional 80C52. 1 machine cycle = 4 clocks vs. 12 clocks Additional peripherals of MiDAS1.0B Family: ...
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... Product Overview A. MiDAS1.0B Family - GC80C521A Series Flash EEPROM RAM Product (byte) (byte) (Byte) GC89C521A0-PQ44I GC89C521A0-QF40I GC89C521A0-LQ32I 8K (1K) 512 GC89C521A0-QF32I GC89C521A0-SO28I (Cont’d) Volt Freq. T/C COMM ADC PWM WDT (V) (MHz) (16bits) I/O (bit x ch) (bit x ch) 10x32 8x16 1 UART 10x32 8x16 24 1.8~5 I2C ...
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Features CPU 8-bit turbo 80C52 architecture 4 cycles/1 machine cycle instruction level compatible with Intel 80C52 8KB FLASH Including 1K User EEPROM 256B Internal AUX. RAM 256B Internal RAM Operating Voltage : 1.8V ~ 5.5V Operating Temperature : -40 ...
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Block Diagram XTAL1 External Osc. 24MHz Ring OSC. 32KHz Ring OSC. TURBO 80C52 CORE POR LVD XTAL2 P0[7:0] P1[7:0] Port Controller Interrupt Controller CPU BUS Timer0 IRAM AUXRAM FLASH WDT Timer1 (256B) (256B) (8KB) (16 ...
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Pin Configurations ADC1.5 / PWM1.5 / INT3 / P1.5 ADC1.6 / PWM1.6 / INT4 / P1.6 ADC1.7 / PWM1.7 / INT5 / P1.7 MDS_SDA / P4.7 / RESET ADC3.0 / PWM3.0 / RXD / P3.0 INT5_A / MOSI / ...
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Pin Configurations ADC1.5 / PWM1.5 / INT3 / P1.5 ADC1.6 / PWM1.6 / INT4 / P1.6 ADC1.7 / PWM1.7 / INT5 / P1.7 MDS_SDA / P4.7 / RESET ADC3.0 / PWM3.0 / RXD / P3.0 ADC3.1 / PWM3.1 / ...
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Pin Configurations ADC1.4 / PWM1.4 / INT2 / P1.4 ADC1.5 / PWM1.5 / INT3 / P1.5 MDS_SDA / RESET ADC3.0 / PWM3.0 / RXD / P3.0 ADC3.1 / PWM3.1 / TXD / P3.1 ADC3.2 / PWM3.2 / INT0 / ...
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Pin Configurations ADC1.0 / PWM1 P1.0 ADC1.1 / PWM1.1 / T2EX / P1.1 ADC1.2 / PWM1.2 / P1.2 ADC1.3 / PWM1.3 / P1.3 MDS_SDA / RESET ADC3.0 / PWM3.0 / RXD / P3.0 ADC3.1 / PWM3.1 ...
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Pin Descriptions Symbol Direction VDD Input Power Supply VSS Input Ground External Reset RESET Input The pull-down resistor is turned on at power-on. XTAL1 Input Input to the inverting oscillator amplifier XTAL2 Output Output from the inverting oscillator amplifier ...
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Pin Descriptions Symbol Direction An 8-bit open-Drain or push-pull I/O port or ADC Input. Note that the output is fully driven (push-pull) when P1 drives PWM1 output. • P1.0 • P1.1 • P1.4 • P1.5 • P1.6 • P1.7 ...
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Pin Descriptions Symbol Direction An 8-bit open-drain or push-pull I/O port or ADC Input. Note that the output is fully driven (push-pull) when P2 drives the high byte of address to access external RAM. • P2.0~P2.7 • P2.0 • ...
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Pin Descriptions Symbol Direction An 8-bit open-drain or push-pull I/O port or ADC Input. • P3.0 • P3.1 • P3.2 • P3.3 • P3.4 • P3.5 • P3.6 • P3.7 • P3.0 • P3.1 • P3.2 • P3.3 P3[7:0] ...
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Pin Descriptions Symbol Direction An 8-bit open-drain or push-pull I/O port. • P4.0 • P4.1 • P4.0 • P4.1 • P4.2 • P4.3 • P4.4 • P4.5 P4[7:0] Input/Output • P4.0 • P4.1 • P4.4 • P4.5 • P4.2 ...
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Memory Organization 1FFFh Internal Flash 0000h 30h Interrupt Vector Lock Flag 20h 18h 10h [ On-chip Program Memory ] 08h (Read/Write with IAP) 00h User can write the data to FLASH or EEPROM with IAP (In-Application Programming). On-chip Data ...
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SFR (Special Function Register) Map Refer to Family Table FFh F0h Internal SFR RAM E8h (Only (Only Direct) Indirect) E0h 80h D8h Internal D0h RAM (Indirect or C8h Direct) C0h 00h B8h B0h A8h A0h 98h 90h 88h 80h ...
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SFR Brief Description 80C52 SFR Registers Register Name ACC Accumulator B B Register PSW Program Status Word SP Stack Pointer DPTR Data Pointer (2 bytes) DPL Low byte DPH High byte P0 Port 0 P1 Port 1 P2 Port ...
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SFR Brief Description Newly added SFR Registers in MiDAS1.0B Family Register Name I2CST I2C Status I2CCON I2C Control I2CCFG I2C Configuration I2CSLA I2C Slave Address I2CDAT I2C Data I2CSCL I2C Clock Scaling SPIST SPI Status SPICON SPI Control SPICK ...
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Instruction Set Summary Refer to Appendix A (Instruction Set) for more details. Type Instruction Addition ADD Addition with Carry ADDC Subtraction with Borrow SUBB Increment INC Arithmetic Decrement DEC Multiply MUL Divide DIV Decimal Adjust DA AND ANL OR ...
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CPU Timing Instruction timing comparison of the MiDAS1.0B family and Intel 80C52 XTAL1 IR ALE CORERIVER PSEN MiDAS1.0B PORT0 INST0 PORT2 ADDH_0 XTAL1 IR Intel 80C52 ALE PSEN PORT0 ADDL_12 PORT2 ADDH_12 INST0 INST1 ADDL_1 INST1 ADDL_2 INST2 ADDH_1 ...
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CPU Timing : MOVX Write XTAL1 IR INST0 INST1 ALE PSEN WR PORT0 INST1 ADDL_1 MOVX PORT2 ADDH_0 ADDH_1 1st Machine Cycle 2nd Machine Cycle 3rd Machine Cycle MOVX Write ...
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CPU Timing : MOVX Reading XTAL1 IR INST0 INST1 ALE PSEN RD PORT0 INST1 ADDL_1 MOVX PORT2 ADDH_0 ADDH_1 1st Machine Cycle 2nd Machine Cycle 3rd Machine Cycle MOVX Read ...
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CPU Timing : Comparison Table The Fastest CPU timing in the world MiDAS1.0B Instruction (CORERIVER) MUL AB 12 clocks DIV AB MOVC A, @A+PC 8 clocks MOVC A, @A+DPTR 8 clocks JMP @A+DPTR RET 8 clocks RETI 4 clocks ...
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I/O Ports : PORT0[7:0] Open-drain (compatible with Intel 8052) or push-pull output, pull-up control, ADC input. During accesses to external memory, the P0 SFR will be automatically set to “FFh”. The alternative functions are available only when the corresponding ...
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I/O Ports : PORT1[7:0] Open-drain or push-pull output, pull-up control, ADC input. The alternative functions are available only when the corresponding SFR bit is “1”. P1.0 = T2, PWM1.0, ADC1.0 / P1.1 = T2EX, PMW1.1, ADC1.1 PWM1.4, ADC1.4 / ...
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I/O Ports : PORT2[7:0] Open-drain or push-pull output, pull-up control, ADC input. During accesses to external memory, the P2 SFR will be automatically set to “FFh”. The alternative functions are available only when the corresponding SFR bit is “1”. ...
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I/O Ports : PORT3[7:0] Open-drain or push-pull output, pull-up control, ADC input. The alternative functions are available only when the corresponding SFR bit is “1”. P3.0 = RXD, PWM3.0, ADC3.0 / P3.1 = TXD, PWM3.1, ADC3.1 P3.4 = T0, ...
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I/O Ports : PORT4[6:0] Open-drain or push-pull output, pull-up control, ADC input. The alternative functions are available only when the corresponding SFR bit is “1”. P4.0 = SSB, I2C_SDA, RXD_A / P4.1 = SCLK,I2C_SCL, TXD_A PWM3.6_A / P4.5 = ...
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I/O Ports : PORT4[7] Open-drain or push-pull output, pull-up control, ADC input. The alternative functions are available only when the corresponding SFR bit is “1”. P4.7 = RESET, MDS_SDA Read-Modify-Write instructions do not read port pin but the port ...
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The ESD Structure of Pads Two ESD diodes and one ESD resister are contained in all pads except VDD. One ESD diode are contained in VDD. [All pads except VDD] • Two ESD Diodes (V • One ESD Resister ...
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LVD (Low Voltage Detector) On-chip power-on reset : 1.6V On-chip power-fail reset : 1.6V Optional power-fail interrupt : 2.2V Flag Transition POF POR POF ...
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WDT (Watchdog Timer) Detects software upset due to external noise or other causes Allows an automatic recovery using WDT interrupt CKCON (8Eh) : Clock Control Register WD2 WD1 WD0 T2M T1M R/W(1) R/W(1) R/W(1) R/W(0) R/W(0) R/W(0) WD[2:0] : ...
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WDT (Watchdog Timer) Block Diagram 27-bit Counter CLK RESET RWT WDCON.0 000 001 WDCON.3 WDIF 010 011 100 512 clocks Delay 101 ...
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Timer/Counter : Timer 0/1 Compatible with traditional 80C52 Timer/Counter Time base is selectable by S clocks or 12 clocks Mode Mode 0 Mode 1 Mode 2 Timer (M1,M0=00) (M1,M0=01) (M1,M0=10) 8-bit T/C Timer0 13-bit T/C 16-bit T/C ...
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Timer/Counter : * Default : F /12 (T0M and T1m is each 0.) OSC F 1/12 OSC 0 1 1/4 CONTROL C/T=0 TxM TLx (5bits) (8bits) Tx PIN C/T=1 TRx GATE INTx PIN [Mode 0] F 1/12 0 OSC ...
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Timer/Counter : Timer 2 Compatible with traditional 80C52 Timer/Counter 2 function Up or down counting selectable by a software Time base is selectable by S clocks or 12 clocks 16-bit Timer/Counter 1. 16-bit Auto-reload With Automatic Reload ...
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Timer/Counter : Timer 2 Mode Description F 1/12 0 OSC 1 1/4 CONTROL C/T2=0 T2M TL2 TH2 T2 PIN C/T2=1 TR2 Capture Transition RCAP2L RCAP2H Detection CONTROL T2EX PIN EXF2 EXEN2 [Capture Mode] (Down Counting Reload Value) 0FFh 0FFh ...
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Timer/Counter : Timer 2 Mode Description F 1/2 OSC CONTROL C/T2=0 TL2 TH2 T2 PIN C/T2=1 TR2 Reload RCAP2L RCAP2H Transition Detection CONTROL T2EX (P1.1) EXEN2 [Baudrate Generator Mode] Timer 1 Overflow 1 SMOD1 1 0 RCLK ...
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Timer/Counter : Timer 2 Mode Description OSC 1/2 CONTROL C/T2=0 TL2 T2 PIN C/T2=1 TR2 BDEN UART RXD Transition Detection CONTROL UART RXD EXF2 EXEN2 [Baud Rate Detector Mode (BDEN = 1)] Support for Baud Rate Detection (T2MOD_BDEN is ...
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UART Function-level compatible with traditional 80C52 UART. Automatic address recognition : Multiprocessor Data Size Mode 0 8 bits 8 data bits 1/4 x Oscillator Clock Start bit(0) 1/32 x Timer 1 Overflow (SMOD1=0) Mode 1 10 bits 8 data ...
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UART : Baudrate Example Serial Port Operating Mode 0 Oscillator Frequency Baudrate = 4 Serial Port Operating Mode 2 2 SMOD1 Baudrate = X 32 EX) Using Timer 1 to Generate Baudrates 2 SMOD1 Mode 1 & 3 Baudrate ...
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UART : Mode 0, Functional Diagram Write to SBUF OSC Serial Port Interrupt REN RI Load SBUF Read SBUF Internal BUS TB8 SBUF CL Zero Detector SHIFT START TX CONTROL SEND TX ...
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UART : Mode 0, Timing Diagram [Transmit ...
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UART : Mode 1, Functional Diagram Timer 1 Timer 2 Overflow Overflow 1 SMOD 0 1 TCLK T2CON RCLK T2CON.5 Internal BUS TB8 Write to SBUF SBUF CL Zero Detector START TX ...
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UART : Mode 1, Timing Diagram [Transmit] TX Clock Write to SBUF S1 SEND Data Shift TXD Start bit TI [Receive] /16 Reset RX CLOCK RXD Start bit Bit Detector Sample Times Shift ...
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UART : Mode 2, Functional Diagram F OSC 1/2 1 SMOD (SMOD is PCON.7) Internal BUS TB8 Write to SBUF SBUF CL Zero Detector STOP BIT START TX CONTROL 1/16 TX CLOCK Serial Port ...
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UART : Mode 2, Timing Diagram [Transmit] TX Clock Write to SBUF SEND S1 Data Shift TXD Start bit TI Stop bit Gen. [Receive] /16 Reset RX CLOCK RXD Start bit Bit Detector Sample Times Shift ...
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UART : Mode 3, Functional Diagram Timer 1 Timer 2 Overflow Overflow 1 SMOD 0 1 TCLK T2CON RCLK T2CON.5 Internal BUS TB8 Write to SBUF SBUF CL Zero Detector START TX ...
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UART : Mode 3, Timing Diagram [Transmit] TX Clock Write to SBUF SEND S1 Data Shift TXD Start bit TI Stop bit Gen. [Receive] /16 Reset RX CLOCK RXD Start bit Bit Detector Sample Times Shift ...
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PWMA (PWM Arrays) PWMA Two 8-bit PWM generation with 8 modules (Compatible to M1.0A 8-bit mode) PWM Data buffer Update (8-bit Counter Overflow Update) PWM Counter can be cleared by S/W. PWM is stopped or started (resumed) by S/W. ...
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PWMA : Block Diagram [PWM Counter] CPS2, Fosc CPS1, CPS0 PWNEN [PWM Module 0] PWMD0 CPU Write Date Overflow PWMCNT PWMOVF PWM Pulse Comp Generation arator PWMD0 Buffer CPU Read Date PWMA Interrupt PWMOEN.0 PWM1.0 (P1.0) MiDAS1.0B Family [52] ...
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PWMA : PWMA0 SFR PWM0CON (92h) : PWMA CH0 Control Register - CPS2 CPS1 CPS0 - - R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) CPS2, CPS1, CPS0 : PWMA counter frequency selection. [0,0, ...
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PWMA : PWMA0 SFR PWM0D0 (94h) : PWMA CH0 Duty Data Register of Module 0 PWMD.7 PWMD.6 PWMD.5 PWMD.4 PWMD.3 PWMD.2 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) Each Module has a internal buffer register for the duty ...
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PWMA : PWMA1 SFR PWM1CON (A2h) : PWMA CH1 Control Register - CPS2 CPS1 CPS0 - - R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) CPS2, CPS1, CPS0 : PWMA counter frequency selection. [0,0, ...
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PWMA : PWMA1 SFR PWM1D0 (A4h) : PWMA CH1 Duty Data Register of Module 0 PWMD.7 PWMD.6 PWMD.5 PWMD.4 PWMD.3 PWMD.2 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) Each Module has a internal buffer register for the duty ...
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PWMA : Pulse Generation Example Clock Count 000h PWM Clock (F /1) OSC PWM Out (PWMxDy = 00h) Low PWM Out 1 Clock Cycle (PWMxDy = 01h) PWM Out (PWMxDy = 80h) (50% Duty) PWM Out (PWMxDy = FFh) ...
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I2C : SFR Two-wire Interface Master or Slave Operation Transmitter or Receiver Operation 100Kbps (Min. Fosc = 1MHz), 400Kbps (Min. Fosc = 4MHz) 7bits / 10bits (Extended 15bits) Address Mode Transfer Wait State Fully Programmable Slave Address SDA/SCL Schmitt-trigger ...
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I2C : SFR (Cont’d) I2CCON (E9h Control Register - SLA2ME SCLHD LASTB PGEN SGEN - R/W(0) R/W(1) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) SLA2ME : 2 nd Byte Slave Address Match Enable in Slave mode [0] ...
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I2C : Block Diagram F : Peripheral Clock PERI Clock F Selection PERI Logic MSSEL I2CIF I2C EI2C Interrupt I2C_CFG I2C_SLA Address Match Detector Address match 8bit Shift Register Fspi Upload I2C_DAT I2C_DAT I2C Control Logic I2C_ST I2C_CON Internal ...
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I2C : Overview Addressing I2C devices 7-bit Address Format MSb 10-bit / Extended 15-bit Address Format MSb S A15 A14 A13 A12 A11 SLA Transfer Acknowledge Slave-Receiver generates an acknowledge bit after Master transfers each byte. ...
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I2C : Overview Master-Transmitter Sequence [7-bit Address Mode] R/W Dat S SLA A A Data a (0) Master-Receiver Sequence [7-bit Address Mode] R/W Dat S SLA A A Data / ( Acknowledge /A : Nor ...
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I2C : Master Transmitter Flow 1. 3. S/W 1) I2CEN = 1 1) I2C_DAT = SLA + R/W(0) Action 2) SGEN = 1 2) I2CIF = 0 S SLA + R/W( I2CS = 1 if the bus ...
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I2C : Master Receiver Flow 1. 3. S/W 1) I2CEN = 1 1) I2C_DAT = SLA + R/W(1) Action 2) SGEN = 1 2) I2CIF = 0 S SLA + R/W( I2CS = 1 if the bus ...
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I2C : Slave Transmitter Flow 1. 3. S/W I2CEN = 1 1) I2C_SLA = SLA 2) I2CIF = 0 Action S SLA + R/W( I2CS = 1 1) I2CRW = 1 2) I2CIF = 1 (if ...
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I2C : Slave Receiver Flow 1. 3. S/W I2CEN = 1 1) I2C_SLA = SLA Action 2) I2CIF = 0 S SLA + R/W( I2CS = 1 1) I2CRW = 0 2) I2CIF = 1 (if ...
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I2C : Master Example I2C Master example code I2CST EQU 0E8H ; I2CST SFR I2CIF EQU 0EFH ; I2CST.7 Flag I2COF EQU 0EEH ; I2CST.6 Flag I2CACK EQU 0EDH ; I2CST.5 Flag I2CRW EQU 0ECH ; I2CST.4 Flag I2CDA ...
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I2C : Slave Example I2C Slave example code using interrupt I2CST EQU 0E8H ; I2CST SFR I2CIF EQU 0EFH ; I2CST.7 Flag I2COF EQU 0EEH ; I2CST.6 Flag I2CACK EQU 0EDH ; I2CST.5 Flag I2CRW EQU 0ECH ; I2CST.4 ...
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SPI : SFR Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Eight Programmable Bit Rates Clock Polarity & Phase Selection Support Write Collision Protection Wake-up from IDLE mode SPIDR (B6h) : ...
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SPI : Block Diagram F : Peripheral Clock PERI Clock F Selection PERI Logic MSSEL CKPOL CKPHA SPICK[2:0] SPIF SPI ESPI SPI Register Interrupt Internal BUS Write SPIDR 8bit Shift Register Fspi (SPI Write Data Buffer) Load SPIDR SPI ...
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SPI : Overview SPI Master-Slave Interconnection Master 8 BIT SHIFT REGISTER CLOCK GENERATOR GPIO SPI Pin Description Pin Description MOSI Master Output Slave Input MISO Master Input Slave Output SCK SPI Clock /SS Slave Select Bar Slave MOSI MOSI ...
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SPI : Mode 0/1 SPI Mode 0 CKPOL = 0 : Leading Edge Rising CKPHA = 0 : Leading Edge Sampling SCK MOSI (Master) / MISO (Slave) MISO (Master) / MOSI (Slave) /SS SPI Mode 1 CKPOL = 0 ...
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SPI : Mode 2/3 SPI Mode 2 CKPOL = 1 : Leading Edge Falling CKPHA = 0 : Leading Edge Sampling SCK MOSI (Master) / MISO (Slave) MISO (Master) / MOSI (Slave) /SS SPI Mode 3 CKPOL = 1 ...
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SPI : Example Master example code SPIST EQU 0C0H SPICON EQU 0B4H SPICK EQU 0B5H SPIDR EQU 0B6H ORG 000h LJMP START ORG 073h ; SPI interrupt routine ANL SPIST, #0FBh ; clear interrupt flag MOV R2, #01h RETI ...
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ADC (Analog-to-Digital Converter) 8-channel 10-bit ADC (SAR Type) Max. 104ksps(samples per sec.) @ FADC = 10MHz & 3V. (Max. 52ksps @ FADC = 5MHz & 3V) ADCON (DEh) : ADC Control & ADC Result Low Register AD_EN AD_REQ AD_END ...
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ADC (Block Diagram) ADCENB0 (CEh) : ADC Channel Enable Bar Register (P0 port) ADCENB0.7 ADCENB0.6 ADCENB0.5 ADCENB0.4 ADCENB0.3 ADCENB0.2 ADCENB0.1 ADCENB0.0 R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W( ADC0 channel ADC0 channel ...
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ADC : Conversion Timing AD_EN Set by S/W AD_REQ Set by S/W AD_END Valid Bit Setup Time 8F ADC ADCF AD_EN : ADC Block Enable Signal. Set or Cleared by S/W. AD_REQ : ADC Conversion Request Start Bit. Set ...
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Interrupt : 14 Sources / 4-level Priority Interrupt Sources : Timer 0/1/2, UART, WDT, ADC, I2C, SPI, 6 External. 4-level Interrupt Priority Timer 0/1/2, UART, ADC, INT0, INT1 2-level Interrupt Priority WDT, I2C, SPI, INT2, INT3, INT4, INT5 [Interrupt ...
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Interrupt Functional Description INT0 IE0 Timer/Counter 0 TF0 INT1 IE1 Timer/Counter 1 TF1 RI UART0 TI Timer/Counter 2 TF2 ADC ADCF INT2 IE2 INT3 IE3 INT4 IE4 INT5 IE5 WDT WDIF I2C I2CF Reserved - SPI SPIF Reserved - ...
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Interrupt : External Interrupt External Interrupt Sources : INT5~0 Support positive edge and negative edge detection Support high level and low level detection IT (B2h) : Interrupt Type Selection Register - - - - IT5 R/W(1) R/W(1) R/W(1) R/W(1) ...
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Reset Circuit : 3 Reset Sources LVD(POR) Reset Power-on Reset when power is turned on. Power-fail Reset when the supply voltage is below the threshold voltage (V ). RST External RESET Pin RESET Pin must be held “High” for ...
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Clock Circuit : SFR System Clock Sources Crystal OSC Oscillator Internal RING OSC Disable of External Clock (Crystal or External Oscillator) If XTOFF is set. When MCU is in stop mode and WDT is not active. Disable of the ...
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Clock Circuit : SFR CKSEL (86h) : Clock Selection Register - - - R32KOE R24MOE - R/W(0) R/W(0) R32KOE : RING 32K port output enable (P0.3) R32MOE : RING 24M port output enable (P0.2) RGPR : WDT clock selection ...
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Clock Circuit : Circuit Diagram RING32K_ON RING32K_ON Internal 32K RINGON RINGON2 RING24M_ON Internal 24M XTOFF WDT_ON PD XTAL_ON XTAL RCLK32 RCLK WDT_ON PD RING_DIV DIV Clock Stable Clock Stable XTUP Counter Counter RGPR 0 1 TS_XTRG RGCLK 0 1 ...
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Clock Circuit : Guideline for Configuration Crystal Oscillator MiDAS XTAL2 XTAL1 Oscillator Module MiDAS XTAL2 XTAL1 OSC Oscillator Module [85] MiDAS1.0B Family ...
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Clock Circuit: Guideline for Using a Crystal Crystal Oscillator & Load Capacitors MiDAS On-chip AMP XTAL2 XTAL1 Crystal Oscillator Load Cap Recommended C Load Cap Graph for Load Capacitor & Frequency L (Load Capacitor) ...
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Power Management : 3 Modes Active Mode : The CPU and The Peripherals operate. Idle Mode : The CPU is gated off from the clock signal. Only the Peripherals operate. Exited by activating any interrupt. The CPU resumes. Exited ...
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ISP & Debugging Code memory (8KBytes) can be programmed using EJTAG in target system. FLASH : 0x0000 ~ 0x1FFF (8,192 Bytes) EEPROM (1KBytes) can be programmed using EJTAG in target system. EEPROM : 0x1C00 ~ 0x1FFF (1,024 Bytes) Debugging ...
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ISP : Command Set Command Blank Check the blank status of the device currently connected. Performs an erase chip, the device’s memory, both code and data. • Code Erase Chip • User data • Information data The device will ...
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IAP ( In Application Programming) Code memory(7KB) & EEPROM(1KB) can be programmed during the operation of MCU. Program time : approximately 3.0 ms Program unit : 1 Byte IAP SFR EEAEN (F7h) : IAP Routine Access Enable Register - ...
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IAP : Function Set IAP call function iap_eeprom_program : call address (FF0Ah) iap_eeprom_erase : call address (FF00h) Before calling IAP function, any interrupt must be disabled. Before calling IAP function, EAEN flag in EEAEN SFR must be set. Only ...
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IAP : Program Flow Init SFR Backup SFR Set IAP Parameter IAP Routine Access Enable Call IAP Routine FLASH_AEN Flag Clear Restore SFR [ Example Code : IAP Program for EEPROM ] ORL EEAEN, #01h ; IAP routine access ...
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IAP : Erase Flow Init SFR Backup SFR Set IAP Parameter IAP Routine Access Enable Call IAP Routine FLASH_AEN Flag Clear Restore SFR [ Example Code : IAP Erase for EEPROM ] ORL EEAEN, #01h ; IAP routine access ...
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Strong Point I : Noise Reduction MiDAS1.0 : ALE “ON” Power Noise 464 mV PP GND Noise 476 mV PP MiDAS1.0 : ALE “OFF” Power Noise 128 mV PP GND Noise 280 mV PP Clock : 22.1184 MHz Company ...
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Strong Point I : Noise Reduction System Clock Noise [MHz] Power 11.0592 Ground Power 22.1184 Ground Power 6 Ground • MiDAS1.0B can reduce EMI by removing the needless swing of ALE signal. • You can enable/disable ALE signal by ...
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Strong Point II : On-Chip POR Conventional MCU + 80C52 10uF RESET 10 kOhms External POR Circuit • On-Chip POR (Power On Reset) can reduce system cost by removing a needless capacitor. • The states of all ports will ...
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Recommended Power Slope The supply voltage slope must be in the range from 0.0V/us to 1.0V/3.2ms. (5V/16ms) (That is, the supply voltage should be increasing monotonically until it reaches to the normal range 500 us ...
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Absolute Maximum Ratings Items Voltage on any pin relative to Ground Voltage in V relative to Ground DD Output Voltage Output Current High Output Current Low Storage Temperature Soldering Temperature Conditions - -0. -0.5V to ...
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DC Characteristics * - + 1.6V ~ 5.5V unless otherwise specified. DD Parameter Symbol V RESETB ,P0, P1, P2, P3, P4 IL1 Input Low Voltage V XTAL1, XTAL2 IL2 ...
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AC Characteristics * unless otherwise specified. Parameter Symbol Operating Frequency F XTAL1, XTAL2 OSC RESETB Input Width t RESET RST External Interrupt t External Interrupt INT Input Width RESET 0.8V ...
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ADC Specifications Parameter Symbol Supply Voltage V DDADC Input Voltage V INADC Resolution RES ADC Operating Frequency F ADC Conversion Time t ADC Overall Accuracy OA ADC Integral Nonlinearity INL ADC Differential Nonlinearity DNL ADC Zero Input Error ZIE ...
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Package Dimensions : PQFP 44 pins 11 12 Seating Plane e 44-PQFP Notes [44-PQFP] Dimension in Inches Dimension ...
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Package Dimensions : TOP VIEW DETAIL SIDE VIEW 40-TQFN D 2 Exposed PAD C0. BOTTOM VIEW 0.203 ±0.008 A Seating Plane 0.00 ...
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Package Dimensions : LQFP 32 pins Seating Plane 32-LQFP Dimension in Inches Dimension ...
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Package Dimensions : TOP VIEW DETAIL SIDE VIEW 32-TQFN D 2 Exposed PAD C0. BOTTOM VIEW 0.203 ±0.008 A Seating Plane 0.00 ...
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Package Dimensions : SOIC 28 pins 1 14 Seating Plane 28-SOIC Notes: A Dimension in Inches Dimension in mm Symbol Min. Nom. ...
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Product Numbering System General Core MCU Series Core Type bits bits bits ROM Type 0 = ROMless 1 = ...
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Supporting tools MDS (Microprocessor Development System) In-Circuit Debugger Easy-to-Use GUI Application System On-board Implemented Various Application Various Sample Test Program Code Generation Tools Assembler & Linker for DOS & Windows Optimized Cross-C Compiler User-Friendly User-Friendly Development Development Environment Environment ...
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Appendix A : instruction set (1/18) ADD A, <src-byte> Add ADD A, Rn Operation : (A) (A) + (Rn) ADD A, @Ri Operation : (A) (A) + ((Ri)) ADD A, direct Operation : (A) (A) + (direct) ADD A, #date ...
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Appendix A : instruction set (2/18) SUBB A, <src-byte> Subtract with Borrow SUBB A, Rn Operation : (A) (A) - (C) - (Rn) SUBB A, @Ri Operation : (A) (A) - (C) - ((Ri)) SUBB A, direct Operation : (A) ...
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Appendix A : instruction set (3/18) DEC <byte> Decrement DEC A Operation : (A) ( DEC Rn Operation : (Rn) (Rn DEC @Ri Operation : ((Ri)) ((Ri DEC direct Operation : (direct) (direct) - ...
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Appendix A : instruction set (4/18 Decimal-adjust Accumulator for Addition )>9] ∨ [(AC)=1]] IF [[(A 3-0 THEN (A Operation : 3-0 )>9] ∨ [(C)=1]] IF [[(A 7-4 THEN (A 7-4 ANL <dest-byte>, <src-byte> Logical AND for byte variables ...
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Appendix A : instruction set (5/18) ANL C, <src-bit> Logical AND for bit variables ANL C, bit Operation : (C) (C) ^ (bit) ANL C, /bit Operation : (C) (C) ^ ~(bit) ORL <dest-byte>, <src-byte> Logical OR for byte variables ...
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Appendix A : instruction set (6/18) ORL C, <src-byte> Logical OR for byte variables ORL C, bit (C) ∨ (bit) Operation : (C) ORL C, /bit (C) ∨ ~(bit) Operation : (C) XRL <dest-byte>, <src-byte> Logical Exclusive-OR for byte variables ...
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Appendix A : instruction set (7/18) CLR A Clear Accumulator Operation : (A) 0 CLR <bit> Clear bit CLR C Operation : (C) 0 CLR bit Operation : (bit) 0 CPL A Complement Accumulator Operation : (A) ~(A) CPL <bit> ...
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Appendix A : instruction set (8/18 Rotate Accumulator Left ( Operation : n RLC A Rotate Accumulator Left through the Carry flag ( n+1 n ...
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Appendix A : instruction set (9/18) MOV <dest-byte>, <src-byte> Move byte variable MOV A, Rn Operation : (A) (Rn) MOV A, @Ri Operation : (A) ((Ri)) MOV A, direct Operation : (A) (direct) MOV A, #date Operation : (A) data ...
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Appendix A : instruction set (10/18) MOV direct, @Ri Operation : (direct) ((Ri)) MOV direct, direct Operation : (direct) (direct) MOV direct, #data Operation : (direct) data MOV @Ri, A Operation : ((Ri)) (A) MOV @Ri, direct Operation : ((Ri)) ...
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Appendix A : instruction set (11/18) MOV DPTR, #data16 Load Data Pointer with a 16-bit constant (DPTR) data Operation : (DPH,DPL) (data MOVC <base-reg> Move Code byte MOVC DPTR Operation : (A) ((A) + ...
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Appendix A : instruction set (12/18) XCH A, <src-byte> Exchange Accumulator with byte variable XCH A, Rn (A) ↔ (Rn) Operation : XCH A, @Ri (A) ↔ ((Ri)) Operation : XCH A, direct (A) ↔ (direct) Operation : XCHD A, ...
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Appendix A : instruction set (13/18) SETB <bit> Set bit SETB C Operation : (C) 1 SETB bit Operation : (bit rel Jump if Carry is set (PC) (PC Operation : If ( then ...
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Appendix A : instruction set (14/18) JBC bit, rel Jump if Bit is set and Clear bit (PC) (PC Operation : If (bit then (bit) 0, (PC) ACALL addr11 Absolute Subroutine Call (PC) (PC ...
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Appendix A : instruction set (15/18) RET Return from Subroutine (PC ) ((SP)) 15-8 (SP) (SP Operation : (PC ) ((SP)) 7-0 (SP) (SP RETI Return from Interrupt (PC ) ((SP)) 15-8 (SP) (SP ...
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Appendix A : instruction set (16/18) JMP @A + DPTR Jump Indirect Relative to the DPTR Operation : (PC) (A) + (DPTR) JZ rel Jump if Accumulator is Zero (PC) (PC Operation : If (A)=0, then (PC) JNZ ...
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Appendix A : instruction set (17/18) CJNE <dest-byte>, <src-byte>, rel Compare and Jump if Not Equal CJNE A, direct, rel (PC) (PC (A) ≠ (direct), Operation : then (PC) If (A) < (direct), then (C) Else CJNE ...
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Appendix A : instruction set (18/18) DJNZ <byte>, rel Decrement and Jump if Not Zero DJNZ Rn, rel (PC) (PC Operation : (Rn) (Rn (Rn)≠0, then (PC) DJNZ direct, rel (PC) (PC (direct) ...
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Appendix B : SFR Description [80h ~ 84h] [How to Read a SFR Descriptions] Yellow Color : Bit Addressable SFR Address White Color : Byte Addressable P0 (80h) : Port 0 Register P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 R/W(1) R/W(1) ...
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Appendix B : SFR Description [85h ~ 88h] ALTSEL (85h) : Port Alternative Function Selection - - - - - EA_IOEN XTAL_IOEN RST_IOEN R/W(0) EA_IOEN : EA IO function enable XTAL_IOEN : XTAL IO function enable RST_IOEN : RESETB IO ...
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Appendix B : SFR Description [89h ~ 8Eh] TMOD (89h) : Timer/Counter 0 Mode Control Register GATE C GATE C/T R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) Timer[1]: GATE[7], C/T[6], M1:M0[5:4] Timer[0]: GATE[3], C/T[2], M1:M0[1:0] GATE : ...
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Appendix B : SFR Description [8Fh ~ 93h] RINGCON (8Fh) : Internal Ring Calibration Control Register RINGC7 RINGC6 RINGC5 RINGC4 RINGC3 RINGC2 RINGC1 RINGC0 R/W(0) R/W(1) R/W(1) R/W(1) R/W(1) R/W(0) P1 (90h) : Port 1 Register P1.7 P1.6 P1.5 P1.4 ...
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Appendix B : SFR Description [94h ~ 99h] PWM0D0 (94h) : PWMA CH0 Duty Data Register of Module 0 PWMD.7 PWMD.6 PWMD.5 PWMD.4 PWMD.3 PWMD.2 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) Each Module has a internal buffer register ...
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Appendix B : SFR Description [9Bh ~ A1h] PWM0OEN (9Bh) : PWMA CH0 Module Output Enable OE7 OE6 OE5 OE4 OE3 OE2 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) OE7 : Module 7 PWM output enable. OE6 : Module ...
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Appendix B : SFR Description [A2h ~ A7h] PWM1CON (A2h) : PWMA CH1 Control Register - CPS2 CPS1 CPS0 - - R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) CPS2, CPS1, CPS0 : PWMA counter frequency selection. [0,0,0] = FOSC ...
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Appendix B : SFR Description [A8h ~ AFh] IE (A8h) : Interrupt Enable Register EA EADC ET2 ES ET1 EX1 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W( Enable/Disable all interrupts. EADC : ADC interrupt enable. ET2 : ...
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Appendix B : SFR Description [B0h ~ B4h] P3 (B0h) : Port 3 Register P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) EIP (B1h) : Extended Interrupt Priority Register PSPI - PI2C PWDT PX5 ...
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Appendix B : SFR Description [B5h ~ B9h] SPICK (B5h) : SPI Clock Control Register - - - - - SPICK2 SPICK1 R/W(0) R/W(0) R/W(0) SPICK[2:0] : SPI Master Clock Divider [0,0,0] : Fosc / 2 [0,0,1] : Fosc / ...
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Appendix B : SFR Description [BAh ~ C4h] ITSEL (BAh) : Interrupt Polarity Selection Register - - ITSEL5 ITSEL4 ITSEL3 ITSEL2 - - R/W(0) R/W(1) R/W(0) R/W(1) R/W(0) R/W(0) ITSEL5 : Interrupt5 Polarity Selection Flag [0] : low level or ...
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Appendix B : SFR Description [C5h ~ CBh] STATUS (C5h) : Crystal Status Register - - - XTUP - - R(0) XTUP : Crystal oscillator warm-up status. This bit is cleared by H/W during executing Power-on reset or during exiting ...
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Appendix B : SFR Description [CCh ~ D2h] TL2 (CCh) : Timer/Counter 2 Low Byte Register TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) TH2 (CDh) : Timer/Counter 2 High Byte Register TH2.7 TH2.6 ...
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Appendix B : SFR Description [D3h ~ D8h] P2SEL (D3h) : Port 2 Pull-up Control Register P2SEL.7 P2SEL.6 P2SEL.5 P2SEL.4 P2SEL.3 P2SEL.2 P2SEL.1 P2SEL.0 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W( Pull-up resistor ON (Default ...
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Appendix B : SFR Description [D9h ~ DFh] P0TYP (D9h) : Port 0 Type Register P0TYPE.7 P0TYPE.6 P0TYPE.5 P0TYPE.4 P0TYPE.3 P0TYPE.2 P0TYPE.1 P0TYPE.0 R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W( Push-pull Output / 1 = Open-drain Output ...
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Appendix B : SFR Description [E0h ~ E4h] ADCS[4:0] : ADC channel selection [00010] : ADC0.2 channel selection. [00011] : ADC0.3 channel selection. [00100] : ADC0.4 channel selection. [00101] : ADC0.5 channel selection. [00110] : ADC0.6 channel selection. [00111] : ...
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Appendix B : SFR Description [E5h ~ E8h] P4DIR (E5h) : Port 4 Input/Output Control Register P4DIR.7 P4DIR.6 P4DIR.5 P4DIR.4 P4DIR.3 P4DIR.2 P4DIR.1 P4DIR.0 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W( Input / 0 = Output (Default). ...
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Appendix B : SFR Description [E9h ~ ECh] I2CCON (E9h) : I2C Control Register - SLA2ME SCLHD LASTB PGEN SGEN R/W(0) R/W(1) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) SLA2ME : 2nd Byte Slave Address Match Enable in Slave mode [0] : ...
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Appendix B : SFR Description [F0h ~ F7h] B (F0h Register B.7 B.6 B.5 B.4 B.3 B.2 R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) R/W(0) EECNTLD (F1h) : EEPROM Erase/Program Time Count Loading EECNTLD - - - - ...
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Appendix C : Update History V1.0 Initial Release V1.1 Modify the ‘Pin Configurations’ slide. Modify the ‘IAP : Function Set’ slide. V1.2 Modify the ‘Clock Circuit’ slide (84 page) Modify the ‘OSCICN SFR Description(138 page) V1.3 Modify the address for ...