mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 344

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

CAN Controller
22.5.2 Receive Structures
Technical Data
342
The second requirement calls for some sort of internal prioritization
which the MSCAN08 implements with the “local priority” concept
described in
The received messages are stored in a 2-stage input first in first out
(FIFO). The two message buffers are mapped using a ping pong
arrangement into a single memory area (see
background receive buffer (RxBG) is exclusively associated to the
MSCAN08, the foreground receive buffer (RxFG) is addressable by the
CPU08. This scheme simplifies the handler software, because only one
address area is applicable for the receive process.
Each buffer has 13 bytes to store the CAN control bits, the identifier
(standard or extended), and the data content (for details, see See
Programmer’s Model of Message
The receiver full flag (RXF) in the MSCAN08 receiver flag register
(CRFLG) (see
status of the foreground receive buffer. When the buffer contains a
correctly received message with matching identifier, this flag is set.
After the MSCAN08 successfully receives a message into the
background buffer, it copies the content of RxBG into RxFG
RXF flag, and emits a receive interrupt to the CPU
which may follow immediately after the IFS field of the CAN frame, will
be received into RxBG.
The user’s receive handler has to read the received message from
RxFG and to reset the RXF flag to acknowledge the interrupt and to
release the foreground buffer.
1. Only if the RXF flag is not set
2. The receive interrupt will occur only if not masked. A polling scheme can be applied on
RXF also.
22.5.2 Receive
22.14.5 MSCAN08 Receiver Flag
CAN Controller
Structures.
Storage.).
Figure
Register) signals the
Freescale Semiconductor
(2)
. A new message,
22-2). While the
MC68HC08QA24
(1)
, sets the
22.13