mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 199

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

16.6.2 Data Direction Register D
MC68HC08QA24
Freescale Semiconductor
NOTE:
NOTE:
Address:
always determine whether reading port D returns the states of the
latches or logic 0.
Do not use ADC channel ATD14 when using the FLT pin as the clock
input for the TIM.
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
DDRD[5:0] — Data Direction Register D Bits
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 16-13
Reset:
Read:
Write:
These read/write bits control port D data direction. Reset clears
DDRD[5:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
$0007
Bit 7
Figure 16-12. Data Direction Register D (DDRD)
R
R
0
0
shows the port D I/O logic.
Input/Output (I/O) Ports
= Reserved
R
6
0
0
DDRD5
5
0
DDRD4
4
0
DDRD3
3
0
DDRD2
2
0
Input/Output (I/O) Ports
DDRD1
Technical Data
1
0
DDRD0
Bit 0
0
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